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R SHUNTV = (I R ) Gain + V OUT LOAD SHUNT REF´Product FolderSample &BuyTechnical Documents Tools &SoftwareSupport &CommunityINA210,INA211,INA212,INA213,INA214,INA215SBOS437G –MAY 2008–REVISED JULY 2014INA21x Voltage Output,Low-or High-Side Measurement,Bidirectional,Zero-Drift Series,Current-Shunt Monitors1Features3DescriptionThe INA210,INA211,INA212,INA213,INA214,and •Wide Common-Mode Range:–0.3V to 26V INA215are voltage-output,current-shunt monitors •Offset Voltage:±35μV (Max,INA210)that can sense drops across shunts at common-mode (Enables Shunt Drops of 10-mV Full-Scale)voltages from –0.3V to 26V,independent of the •Accuracy:supply voltage.Five fixed gains are available:50V/V,75V/V,100V/V,200V/V,500V/V,or 1000V/V.The –±1%Gain Error (Max over Temperature)low offset of the zero-drift architecture enables –0.5-μV/°C Offset Drift (Max)current sensing with maximum drops across the –10-ppm/°C Gain Drift (Max)shunt as low as 10-mV full-scale.•Choice of Gains:These devices operate from a single 2.7-V to 26-V –INA210:200V/V power supply,drawing a maximum of 100μA of supply current.All versions are specified over the –INA211:500V/V extended operating temperature range (–40°C to –INA212:1000V/V 125°C),and offered in an SC70package.The –INA213:50V/V INA210,INA213,and INA214are also offered in a thin UQFN package.–INA214:100V/V –INA215:75V/VDevice Information (1)•Quiescent Current:100μA (max)PART NUMBER PACKAGE BODY SIZE (NOM)•SC70Package:All ModelsSC70(6) 2.00mm ×1.25mm INA210•Thin UQFN Package:INA210,INA213,INA214UQFN (10) 1.80mm ×1.40mm INA211SC70(6) 2.00mm ×1.25mm 2ApplicationsINA212SC70(6) 2.00mm ×1.25mm •Notebook Computers SC70(6) 2.00mm ×1.25mm INA213•Cell PhonesUQFN (10) 1.80mm ×1.40mm •Telecom Equipment SC70(6) 2.00mm ×1.25mm INA214UQFN (10) 1.80mm ×1.40mm •Power Management INA215SC70(6)2.00mm ×1.25mm•Battery Chargers (1)For all available packages,see the orderable addendum at•Welding Equipmentthe end of the datasheet.Simplified SchematicINA210,INA211,INA212,INA213,INA214,INA215SBOS437G–MAY2008–REVISED Table of Contents8.3Feature Description (13)1Features (1)8.4Device Functional Modes (14)2Applications (1)9Application and Implementation (20)3Description (1)9.1Application Information (20)4Revision History (2)9.2Typical Applications (20)5Device Options (4)10Power Supply Recommendations (23)6Pin Configurations and Functions (4)11Layout (23)7Specifications (5)11.1Layout Guidelines (23)7.1Absolute Maximum Ratings (5)11.2Layout Example (23)7.2Handling Ratings (5)12Device and Documentation Support (24)7.3Recommended Operating Conditions (6)12.1Documentation Support (24)7.4Thermal Information (6)12.2Related Links (24)7.5Electrical Characteristics (6)12.3Trademarks (24)7.6Typical Characteristics (8)12.4Electrostatic Discharge Caution (24)8Detailed Description (12)12.5Glossary (24)8.1Overview (12)13Mechanical,Packaging,and Orderable8.2Functional Block Diagram (12)Information (24)4Revision HistoryNOTE:Page numbers for previous revisions may differ from page numbers in the current version.Changes from Revision F(June2014)to Revision G Page •Changed Simplified Schematic:added equation below gain table (1)•Changed V(ESD)HBM specifications for version A in Handling Ratings table (5)Changes from Revision E(June2013)to Revision F Page •Changed format to meet latest data sheet standards;added Pin Functions,Recommended Operating Conditions, and Thermal Information tables,Overview,Functional Block Diagram,Application Information,Power SupplyRecommendations,and Layout sections,and moved existing sections (1)•Added INA215to document (1)•Added INA215sub-bullet to fourth Features bullet (1)•Added INA215to simplified schematic table (1)•Changed title of Device Options table (4)•Added Thermal Information table (5)•Added INA215to Figure7 (8)•Added INA215to Figure15 (9)•Added INA215to Figure25 (16)Changes from Revision D(November2012)to Revision E Page •Deleted Package Marking column from Package/Ordering Information table (4)Changes from Revision C(August2012)to Revision D Page •Changed Frequency Response,Bandwidth parameter in Electrical Characteristics table (5)2Submit Documentation Feedback Copyright©2008–2014,Texas Instruments IncorporatedINA210,INA211,INA212,INA213,INA214,INA215 SBOS437G–MAY2008–REVISED JULY2014Changes from Revision B(June2009)to Revision C Page•Changed Package/Ordering table to show both silicon versions A and B (4)•Added silicon version B ESD ratings to Abs Max table (5)•Added silicon version B row to Input,Common-Mode Input Range parameter in Electrical Characteristics table (5)•Corrected typo in Figure9 (8)•Updated Figure12 (8)•Changed Input Filtering section (14)•Added Improving Transient Robustness section (19)Changes from Revision A(June2008)to Revision B Page•Added RSW package to device photo (1)•Added UQFN package to Features list (1)•Updated front page graphic (1)•Added RSW ordering information to Package/Ordering Information table (4)•Added RSW package pin out drawing (4)•Added footnote3to Electrical Characteristics table (5)•Added UQFN package information to Temperature Range section of Electrical Characteristics table (5)•Changed Figure2to reflect operating temperature range (8)•Changed Figure4to reflect operating temperature range (8)•Changed Figure6to reflect operating temperature range (8)•Changed Figure13to reflect operating temperature range (9)•Changed Figure14to reflect operating temperature range (9)•Added RSW description to the Basic Connections section (13)•Changed60μV to100μV in last sentence of the Selecting RS section (13)Changes from Original(May2008)to Revision A Page•Changed availability of INA211and INA212to currently available in Package/Ordering Information table (4)•Deleted first footnote of Electrical Characteristics table (5)•Changed Figure7 (8)•Changed Figure15 (9)Copyright©2008–2014,Texas Instruments Incorporated Submit Documentation Feedback3NC (1)V+NC(1)IN+IN+IN -IN -REF89105431276GND OUT123654OUT IN -IN+REF GND V+INA210,INA211,INA212,INA213,INA214,INA215SBOS437G –MAY 2008–REVISED JULY 20145Device OptionsPACKAGE PRODUCT GAIN (V/V)PACKAGE DESIGNATOR200SC70-6DCK INA210A 200Thin UQFN-10RSW 200SC70-6DCK INA210B 200Thin UQFN-10RSW INA211A 500SC70-6DCK INA211B 500SC70-6DCK INA212A 1000SC70-6DCK INA212B 1000SC70-6DCK 50SC70-6DCK INA213A 50Thin UQFN-10RSW 50SC70-6DCK INA213B 50Thin UQFN-10RSW 100SC70-6DCK INA214A 100Thin UQFN-10RSW 100SC70-6DCK INA214B 100Thin UQFN-10RSW INA215A75SC70-6DCK6Pin Configurations and FunctionsDCK PackageRSW Package SC70-6Thin UQFN-10(Top View)(Top View)(1)NC denotes no internal connection.These pins can be left floating or connected to any voltage between V–and V+.4Submit Documentation Feedback Copyright ©2008–2014,Texas Instruments IncorporatedINA210,INA211,INA212,INA213,INA214,INA215 SBOS437G–MAY2008–REVISED JULY2014Pin FunctionsPINNO.I/O DESCRIPTIONNAMEDCK RSWGND29Analog GroundAnalogIN–54,5Connect to load side of shunt resistor.inputAnalogIN+42,3Connect to supply side of shunt resistorinputNC—1,7—Not internally connected.Leave floating or connect to ground.AnalogOUT610Output voltageoutputAnalogREF18Reference voltage,0V to V+inputV+36Analog Power supply,2.7V to26V7Specifications7.1Absolute Maximum Ratings(1)over operating free-air temperature range(unless otherwise noted)MIN MAX UNIT Supply voltage,V S26VDifferential(V IN+)–(V IN–)–2626VAnalog inputs,V IN+,V IN–(2)Common-mode(3)GND–0.326VREF input GND–0.3(V S)+0.3VOutput(3)GND–0.3(V S)+0.3VInput current into any terminal(3)5mA Operating temperature–55150°C Junction temperature150°C(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratingsonly,which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)V IN+and V IN–are the voltages at the IN+and IN–terminals,respectively.(3)Input voltage at any terminal may exceed the voltage shown if the current at that terminal is limited to5mA.7.2Handling RatingsMIN MAX UNITT stg Storage temperature range–65150°CHuman body model(HBM)ESD stress voltage(1)–20002000 Electrostatic dischargeV(ESD)Charged-device model(CDM)ESD stress voltage(2)–10001000V (version A)Machine model(MM)ESD stress voltage–200200Human body model(HBM)ESD stress voltage(1)–15001500 Electrostatic dischargeV(ESD)Charged-device model(CDM)ESD stress voltage(2)–10001000V (version B)Machine model(MM)ESD stress voltage–100100(1)JEDEC document JEP155states that500-V HBM allows safe manufacturing with a standard ESD control process.(2)JEDEC document JEP157states that250-V CDM allows safe manufacturing with a standard ESD control process.Copyright©2008–2014,Texas Instruments Incorporated Submit Documentation Feedback5INA210,INA211,INA212,INA213,INA214,INA215SBOS437G–MAY2008–REVISED 7.3Recommended Operating Conditionsover operating free-air temperature range(unless otherwise noted)MIN NOM MAX UNITV CM Common-mode input voltage12VV S Operating supply voltage5VT A Operating free-air temperature–40125°C7.4Thermal InformationINA210-INA215THERMAL METRIC(1)DCK(SC70)RSW(UQFN)UNIT6PINS10PINSRθJA Junction-to-ambient thermal resistance227.3107.3RθJC(top)Junction-to-case(top)thermal resistance79.556.5RθJB Junction-to-board thermal resistance72.118.7°C/WψJT Junction-to-top characterization parameter 3.6 1.1ψJB Junction-to-board characterization parameter70.418.7RθJC(bot)Junction-to-case(bottom)thermal resistance n/a n/a(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.7.5Electrical CharacteristicsAt T A=25°C,V SENSE=V IN+–V IN–.INA210,INA213,INA214,and INA215:V S=5V,V IN+=12V,and V REF=V S/2,unless otherwise noted.INA211and INA212:V S=12V,V IN+=12V,and V REF=V S/2,unless otherwise noted.PARAMETER CONDITIONS MIN TYP MAX UNIT INPUTVersion A,T A=–40°C to125°C–0.326VV CM Common-mode input rangeVersion B,T A=–40°C to125°C–0.126VINA210,INA211,V IN+=0V to26V,V SENSE=0mV,INA212,INA214,105140dBT A=–40°C to125°CCommon-mode INA215CMRRrejection ratioV IN+=0V to26V,V SENSE=0mV,INA213100120dBT A=–40°C to125°CINA210,INA211,V SENSE=0mV±0.55±35μVINA212V O Offset voltage,RTI(1)INA213V SENSE=0mV±5±100μVINA214,INA215V SENSE=0mV±1±60μVdV OS/dT RTI vs temperature V SENSE=0mV,T A=–40°C to125°C0.10.5μV/°CV S=2.7V to18V,V IN+=18V,PSRR RTI vs power supply ratio±0.1±10μV/VV SENSE=0mVI IB Input bias current V SENSE=0mV152835μAI IO Input offset current V SENSE=0mV±0.02μA OUTPUTINA210200V/VINA211500V/VINA2121000V/VG GainINA21350V/VINA214100V/VINA21575V/VV SENSE=–5mV to5mV,E G Gain error±0.02%±1%T A=–40°C to125°CGain error vs temperature T A=–40°C to125°C310ppm/°CNonlinearity error V SENSE=–5mV to5mV±0.01%Maximum capacitive load No sustained oscillation1nF (1)RTI=referred-to-input.6Submit Documentation Feedback Copyright©2008–2014,Texas Instruments IncorporatedINA210,INA211,INA212,INA213,INA214,INA215 SBOS437G–MAY2008–REVISED JULY2014Electrical Characteristics(continued)At T A=25°C,V SENSE=V IN+–V IN–.INA210,INA213,INA214,and INA215:V S=5V,V IN+=12V,and V REF=V S/2,unless otherwise noted.INA211and INA212:V S=12V,V IN+=12V,and V REF=V S/2,unless otherwise noted.PARAMETER CONDITIONS MIN TYP MAX UNIT VOLTAGE OUTPUT(2)R L=10kΩto GND,T A=–40°C toSwing to V+power-supply rail(V+)–0.05(V+)–0.2V125°CR L=10kΩto GND,T A=–40°C toSwing to GND(V GND)+0.005(V GND)+0.05V125°CFREQUENCY RESPONSEC LOAD=10pF,INA21014kHzC LOAD=10pF,INA2117kHzC LOAD=10pF,INA2124kHz BW BandwidthC LOAD=10pF,INA21380kHzC LOAD=10pF,INA21430kHzC LOAD=10pF,INA21540kHzSR Slew rate0.4V/μs NOISE,RTI(1)Voltage noise density25nV/√Hz POWER SUPPLYV S Operating voltage range T A=–40°C to125°C 2.726VI Q Quiescent current V SENSE=0mV65100μAI Q over temperature T A=–40°C to125°C115μA TEMPERATURE RANGESpecified range–40125°COperating range–55150°CSC70250°C/WθJA Thermal resistanceThin UQFN80°C/W (2)See Typical Characteristic curve,Output Voltage Swing vs Output Current(Figure10).Copyright©2008–2014,Texas Instruments Incorporated Submit Documentation Feedback7INA210,INA211,INA212,INA213,INA214,INA215SBOS437G–MAY2008–REVISED 7.6Typical CharacteristicsThe INA210is used for typical characteristics at T A=25°C,V S=5V,V IN+=12V,and V REF=V S/2,unless otherwise noted.8Submit Documentation Feedback Copyright©2008–2014,Texas Instruments IncorporatedINA210,INA211,INA212,INA213,INA214,INA215 SBOS437G–MAY2008–REVISED JULY2014Typical Characteristics(continued)Copyright©2008–2014,Texas Instruments Incorporated Submit Documentation Feedback9INA210,INA211,INA212,INA213,INA214,INA215SBOS437G–MAY2008–REVISED Typical Characteristics(continued)10Submit Documentation Feedback Copyright©2008–2014,Texas Instruments IncorporatedTypical Characteristics(continued)IN-GNDV+8.1OverviewThe INA210-INA215are 26-V,common-mode,zero-drift topology,current-sensing amplifiers that can be used in both low-side and high-side configurations.These specially-designed,current-sensing amplifiers are able to accurately measure voltages developed across current-sensing resistors on common-mode voltages that far exceed the supply voltage powering the device.Current can be measured on input voltage rails as high as 26V while the device can be powered from supply voltages as low as 2.7V.The zero-drift topology enables high-precision measurements with maximum input offset voltages as low as 35µV with a maximum temperature contribution of 0.5µV/°C over the full temperature range of –40°C to 125°C.8.2Functional Block DiagramPower Supply8.3.1Basic ConnectionsFigure 23shows the basic connections of the INA210-INA215.The input pins,IN+and IN–,should be connected as closely as possible to the shunt resistor to minimize any resistance in series with the shunt resistor.Figure 23.Typical ApplicationPower-supply bypass capacitors are required for stability.Applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.Connect bypass capacitors close to the device pins.On the RSW package options,two pins are provided for each input.These pins should be tied together (that is,tie IN+to IN+and tie IN–to IN–).8.3.2Selecting R SThe zero-drift offset performance of the INA210-INA215offers several benefits.Most often,the primary advantage of the low offset characteristic enables lower full-scale drops across the shunt.For example,non-zero-drift current shunt monitors typically require a full-scale range of 100mV.The INA210-INA215series gives equivalent accuracy at a full-scale range on the order of 10mV.This accuracy reduces shunt dissipation by an order of magnitude with many additional benefits.Alternatively,there are applications that must measure current over a wide dynamic range that can take advantage of the low offset on the low end of the measurement.Most often,these applications can use the lower gains of the INA213,INA214or INA215to accommodate larger shunt drops on the upper end of the scale.For instance,an INA213operating on a 3.3-V supply could easily handle a full-scale shunt drop of 60mV,with only 100μV of offset.Gain Error Factor =(1250´INTR)(1250S´´´R) + (1250R) + (R R)INT S INTRV+8.4Device Functional Modes8.4.1Input FilteringAn obvious and straightforward filtering location is at the device output.However,this location negates the advantage of the low output impedance of the internal buffer.The only other filtering option is at the device input pins.This location,though,does require consideration of the±30%tolerance of the internal resistances. Figure24shows a filter placed at the inputs pins.Figure24.Filter at Input PinsThe addition of external series resistance,however,creates an additional error in the measurement so the value of these series resistors should be kept to10Ωor less if possible to reduce impact to accuracy.The internal bias network shown in Figure24present at the input pins creates a mismatch in input bias currents when a differential voltage is applied between the input pins.If additional external series filter resistors are added to the circuit,the mismatch in bias currents results in a mismatch of voltage drops across the filter resistors.This mismatch creates a differential error voltage that subtracts from the voltage developed at the shunt resistor.This error results in a voltage at the device input pins that is different than the voltage developed across the shunt resistor.Without the additional series resistance,the mismatch in input bias currents has little effect on device operation.The amount of error these external filter resistor add to the measurement can be calculated using Equation2where the gain error factor is calculated using Equation1.The amount of variance in the differential voltage present at the device input relative to the voltage developed at the shunt resistor is based both on the external series resistance value as well as the internal input resistors,R3 and R4(or R INT as shown in Figure24).The reduction of the shunt voltage reaching the device input pins appears as a gain error when comparing the output voltage relative to the voltage across the shunt resistor.A factor can be calculated to determine the amount of gain error that is introduced by the addition of external series resistance.The equation used to calculate the expected deviation from the shunt voltage to what is seen at the device input pins is given in Equation1:where:•R INT is the internal input resistor(R3and R4),and•R S is the external series resistance.(1)Gain Error (%) = 100(100Gain Error Factor)-´Device Functional Modes (continued)With the adjustment factor equation including the device internal input resistance,this factor varies with each gain version,as shown in Table 1.Each individual device gain error factor is shown in Table 2.Table 1.Input ResistancePRODUCT GAIN R INT (k Ω)INA2102005INA2115002INA21210001INA2135020INA21410010INA2157513.3Table 2.Device Gain Error FactorThe gain error that can be expected from the addition of the external series resistors can then be calculatedbased on Equation 2:(2)For example,using an INA212and the corresponding gain error equation from Table 2,a series resistance of 10Ωresults in a gain error factor of 0.982.The corresponding gain error is then calculated using Equation 2,resulting in a gain error of approximately 1.77%solely because of the external 10-Ωseries ing an INA213with the same 10-Ωseries resistor results in a gain error factor of 0.991and a gain error of 0.84%again solely because of these external resistors.Control8.4.2Shutting Down the INA210-INA215SeriesWhile the INA210-INA215series does not have a shutdown pin,its low power consumption allows powering from the output of a logic gate or transistor switch that can turn on and turn off the INA210-INA215power-supply quiescent current.However,in current shunt monitoring applications.there is also a concern for how much current is drained from the shunt circuit in shutdown conditions.Evaluating this current drain involves considering the simplified schematic of the INA210-INA215in shutdown mode shown in Figure 25.NOTE:1-M Ωpaths from shunt inputs to reference and INA21x outputs.Figure 25.Basic Circuit for Shutting Down the INA210-INA215with a Grounded ReferenceNote that there is typically slightly more than 1-M Ωimpedance (from the combination of 1-M Ωfeedback and 5-k Ωinput resistors)from each input of the INA210-INA215to the OUT pin and to the REF pin.The amount of current flowing through these pins depends on the respective ultimate connection.For example,if the REF pin is grounded,the calculation of the effect of the 1-M Ωimpedance from the shunt to ground is straightforward.However,if the reference or op amp is powered while the INA210-INA215is shut down,the calculation is direct;instead of assuming 1M Ωto ground,however,assume 1M Ωto the reference voltage.If the reference or op amp is also shut down,some knowledge of the reference or op amp output impedance under shutdown conditions is required.For instance,if the reference source behaves as an open circuit when is not powered,little or no current flows through the 1-M Ωpath.Regarding the 1-M Ωpath to the output pin,the output stage of a disabled INA210-INA215does constitute a good path to ground;consequently,this current is directly proportional to a shunt common-mode voltage impressed across a 1-M Ωresistor.As a final note,when the device is powered up,there is an additional,nearly constant,and well-matched 25μA that flows in each of the inputs as long as the shunt common-mode voltage is 3V or higher.Below 2-V common-mode,the only current effects are the result of the 1-M Ωresistors.8.4.3REF Input Impedance EffectsAs with any difference amplifier,the INA210-INA215series common-mode rejection ratio is affected by any impedance present at the REF input.This concern is not a problem when the REF pin is connected directly to most references or power supplies.When using resistive dividers from the power supply or a reference voltage, the REF pin should be buffered by an op amp.In systems where the INA210-INA215output can be sensed differentially,such as by a differential input analog-to-digital converter(ADC)or by using two separate ADC inputs,the effects of external impedance on the REF input can be cancelled.Figure26depicts a method of taking the output from the INA210-INA215by using the REF pin as a reference.Figure26.Sensing the INA210-INA215to Cancel the Effects of Impedance on the REF Input8.4.4Using The INA210-INA215with Common-Mode Transients Above26VWith a small amount of additional circuitry,the INA210-INA215series can be used in circuits subject to transients higher than26V,such as automotive e only zener diode or zener-type transient absorbers (sometimes referred to as Transzorbs)—any other type of transient absorber has an unacceptable time delay. Start by adding a pair of resistors as a working impedance for the zener;see Figure27.Keeping these resistors as small as possible is preferable,most often around10Ω.Larger values can be used with an effect on gain that is discussed in the Input Filtering section.Because this circuit is limiting only short-term transients,many applications are satisfied with a10-Ωresistor along with conventional zener diodes of the lowest power rating that can be found.This combination uses the least amount of board space.These diodes can be found in packages as small as SOT-523or SOD-523.Shutdown Control RShutdownControlRFigure27.INA210-INA215Transient Protection using Dual Zener DiodesIn the event that low-power zeners do not have sufficient transient absorption capability and a higher power transzorb must be used,the most package-efficient solution then involves using a single transzorb and back-to-back diodes between the device inputs.The most space-efficient solutions are dual series-connected diodes in a single SOT-523or SOD-523package.This method is shown in Figure28.In either of these examples,the total board area required by the INA210-INA215with all protective components is less than that of an SO-8package, and only slightly greater than that of an MSOP-8package.Figure28.INA210-INA215Transient Protection using a Single Transzorb and Input Clamps+2.7V to +26VReference VoltageShuntSupplyOutput8.4.5Improving Transient RobustnessApplications involving large input transients with excessive dV/dt above 2kV per microsecond present at the device input pins may cause damage to the internal ESD structures on version A devices.This potential damage is a result of the internal latching of the ESD structure to ground when this transient occurs at the input.With significant current available in most current-sensing applications,the large current flowing through the input transient-triggered,ground-shorted ESD structure quickly results in damage to the silicon.External filtering can be used to attenuate the transient signal prior to reaching the inputs to avoid the latching condition.Care must be taken to ensure that external series input resistance does not significantly impact gain error accuracy.For accuracy purposes,these resistances should be kept under 10Ωif possible.Ferrite beads are recommended for this filter because of their inherently low dc ohmic value.Ferrite beads with less than 10Ωof resistance at dc and over 600Ωof resistance at 100MHz to 200MHz are recommended.The recommended capacitor values for this filter are between 0.01µF and 0.1µF to ensure adequate attenuation in the high-frequency region.This protection scheme is shown in Figure 29.Figure 29.Transient ProtectionTo minimize the cost of adding these external components to protect the device in applications where large transient signals may be present,version B devices are now available with new ESD structures that are not susceptible to this latching condition.Version B devices are incapable of sustaining these damage causing latched conditions so they do not have the same sensitivity to the transients that the version A devices have,thus making the version B devices a better fit for these applications.BYPASS 0.1µF9Application and Implementation9.1Application InformationThe INA210-INA215measure the voltage developed across a current-sensing resistor when current passes through it.The ability to drive the reference pin to adjust the functionality of the output signal offers multiple configurations,as discussed throughout this section.9.2Typical Applications9.2.1Unidirectional OperationFigure 30.Unidirectional Application Schematic9.2.1.1Design RequirementsThe device can be configured to monitor current flowing in one direction (unidirectional)or in both directions (bidirectional)depending on how the REF pin is configured.The most common case is unidirectional where the output is set to ground when no current is flowing by connecting the REF pin to ground,as shown in Figure 30.When the input signal increases,the output voltage at the OUT pin increases.9.2.1.2Detailed Design ProcedureThe linear range of the output stage is limited in how close the output voltage can approach ground under zero input conditions.In unidirectional applications where measuring very low input currents is desirable,bias the REF pin to a convenient value above 50mV to get the output into the linear range of the device.To limit common-mode rejection errors,TI recommends buffering the reference voltage connected to the REF pin.A less frequently-used output biasing method is to connect the REF pin to the supply voltage,V+.This method results in the output voltage saturating at 200mV below the supply voltage when no differential input signal is present.This method is similar to the output saturated low condition with no input signal when the REF pin is connected to ground.The output voltage in this configuration only responds to negative currents that develop negative differential input voltage relative to the device IN–pin.Under these conditions,when the differential input signal increases negatively,the output voltage moves downward from the saturated supply voltage.The voltage applied to the REF pin must not exceed the device supply voltage.。

22B112A(ShadowMoiree)

the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer
JESD22-B108A measures device terminal coplanarity only at room temperature and cannot be used to predict warpage at elevated temperatures. The worst-case warpage may be at room temperature, maximum reflow temperature, or any temperature in-between; consequently, package warpage must be characterized during the entire reflow soldering thermal cycle. Critical engineering evaluations of the package and printed circuit board warpage should be conducted in the laboratory under simulated reflow conditions. For many packages, warpage can change with continued reflow cycles so this measurement should be made and reported for the first reflow cycle.

AIMB-210

Temperature Dimensions
* Minimum order quantity is required.
Industrial Motherboards
All product specifications are subject to change without notice Last updated : 09-Nov-2009
GbE LAN1: Realtek 8111C GbE LAN2: Realtek 8111C PCI
USB 2.0/1.1
HD Audio
ICH7M
PCIe x1
32-bit/33MHz PCI Bus SM Bus
LPC
Super IO Winbond W83627DHG
Fintek F81216D 4 RS-232
Online Download /products
Value-Added Software Services
Software API: An interface that defines the ways by which an application program may request services from libraries and/or operating systems. Provides not only the underlying drivers required but also a rich set of user-friendly, intelligent and integrated interfaces, which speeds development, enhances security and offers add-on value for Advantech platforms. It plays the role of catalyst between developer and solution, and makes Advantech embedded platforms easier and simpler to adopt and operate with customer applications.

NAU8822A_Design_Guide_Rev_2.0

Headphones/ Line drivers AUXOUT2 AUXOUT1 LHP RHP BTL Speaker LSPKOUT RSPKOUT
5-band EQ 3D
NAU8822AYG
NAU8822A Data Preliminary Rev 2.0
Page 1 of 89
January 25, 2011
CSB/GPIO1
VDDC
MCLK
DACIN
VDDB
VSSD
SCLK
Part Number NAU8822AYG
Dimension 5 x 5 mm
Package 32-QFN
Package Material Pb-Free
NAU8822A Design Guide Rev 2.0
Page 2 of 89
VSSSPK RSPKOUT AUXOUT2 AUXOUT1 RAUXIN LAUXIN MODE SDIO
RMICP RMICN
RLIN/GPIO3
NAU8822AYG 32-lead QFN RoHS
22 22 21 21 20 20 19 19 18 18 17 17
FS BCLK
ADCOUT
emPowerAudio™
Applications Personal Media Players Smartphones Personal Navigation Devices Portable Game Players Camcorders Digital Still Cameras Portable TVs Stereo Bluetooth Headsets
LAUXIN RAUXIN LLIN RLIN LMICN LMICP RMICN RMICP Digital Audio Interface Microphone Bias GPIO PLL I2S PCM Serial Control Interface Stereo Microphone Interface Input Mixer RADC LADC ADC Filter Volume Control High Pass & Notch Filters DAC Filter Volume Control Limiter RDAC Output Mixer LDAC

MF210

HSUPA PCI Express Mini Card MF210开发文档Revision1.2February 23, 2009产品名称：MF210公司名称：中兴通讯股份有限公司目录1概述 (2)2.执行标准 (2)3.技术说明 (3)3.1工作频段 (3)3.2承载业务 (3)3.3硬件技术参数 (4)4. 接口定义 (5)4.1 PCI Express Mini Card Specification (5)4.2 PIN Definition (5)5射频测试座 (6)5.1 射频测试座规格 (6)5.2 射频连接线 (6)5.3 主天线和分集连接器位置 (7)5.4射频测试座S参数测试 (7)5.4.1 主天线射频座技术参数 (7)5.4.2 分集天线射频座技术参数 (8)6．射频主要性能指标 (9)6.1 UMTS模式射频技术指标 (9)6.1.1最大发射功率 (9)6.1.2接收灵敏度 (9)6.2 GPRS/GSM/EDGE模式射频技术指标 (10)6.2.1发射输出功率 (10)6.2.2接收灵敏度 (10)7.天线 (11)7.1无源指标（推荐） (11)7.2有源指标（推荐） (11)7.3笔记本布局建议 (11)7.4天线尺寸及放置 (12)7.5分集天线设计 (12)1概述MF210是一款支持UMTS850（900）/1900/2100、GSM/GPRS/EDGE 850/900/1800/1900多频段HSUPA的PCI Express Mini Card无线网卡，可以提供移动环境下的WCDMA、GSM/GPRS、EDGE（EGPRS）和HSUPA高速数据接入服务。

注：UMTS850和UMTS900不能同时支持图1.1. MF210实物图2.执行标准[1] PCI Express Mini Card Electromechanical Specification Revision 1.2，October26 2007[2] 3GPP TS 34.121 User Equipment (UE) conformance specification; Radio transmission and reception (FDD)[3] 3GPP TS 05.05[4] 3GPP TS 34.124 Electromagnetic compatibility (EMC) requirements for Mobile terminals and ancillary equipment3.技术说明3.1工作频段HSUPA PCI Express Mini Card MF210网卡的工作频段如表3-1所示。

AFUWIN

AFUWINAMIBIOS8 ROM Utility User GuideAFUWINDocument Revision 1.0.1 – Aug 28, 2009NDA REQUIREDCopyright (c) 2008 American Megatrends, Inc.All Rights Reserved.American Megatrends, Inc.5555 Oakbrook ParkwaySuite 200Norcross, GA 30093This publication contains proprietary information which is protected by copyright. No part of this publication may be reproduced, transcribed, stored in a retrieval system, translated into any language or computer language, or transmitted in any form whatsoever without the prior written consent of the publisher, American Megatrends, Inc. American Megatrends, Inc. retains the right to update, change, modify this publication at any time, without notice. For Additional InformationCall American Megatrends BIOS Sales Department at 1-800-828-9264 for additional information.Limitations of LiabilityIn no event shall American Megatrends be held liable for any loss, expenses, or damages of any kind whatsoever, whether direct, indirect, incidental, or consequential, arising from the design or use of this product or the support materials provided with the product.Limited WarrantyNo warranties are made, either express or implied, with regard to the contents of this work, its merchantability, or fitness for a particular use. American Megatrends assumes no responsibility for errors and omissions or for the uses made of the material contained herein or reader decisions based on such use.Trademark and Copyright AcknowledgmentsAll product names used in this publication are for identification purposes only and are trademarks of their respective Companies.DisclaimerThis manual describes the operation of the AMIBIOS8 ROM Utilities. Although efforts have been made to insure the accuracy of the information contained here, American Megatrends expressly disclaims liability for any error in this information, and for damages, whether direct, indirect, special, exemplary, consequential or otherwise, that may result from such error, including but not limited to the loss of profits resulting from the use or misuse of the manual or information contained therein (even if American Megatrends has been advised of the possibility of such damages). Any questions or comments regarding this document or its contents should be addressed to American Megatrends at the address shown on the cover.American Megatrends provides this publication “as is” without warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of merchantability or fitness for a specific purpose.Some states do not allow disclaimer of express or implied warranties or the limitation or exclusion of liability for indirect, special, exemplary, incidental or consequential damages in certain transactions; therefore, this statement may not apply to you. Also, you may have other rights which vary from jurisdiction to jurisdiction.This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the publication. American Megatrends may make improvements and/or revisions in the product(s) and/or the program(s) described in this publication at any time. Requests for technical information about American Megatrends products should be made to your American Megatrends authorized reseller or marketing representative.Revision InformationOverviewAFUWIN is an updating system BIOS utility with command line and GUI interface. It has same parameters and behavior as AFUWIN, and further, GUI feature starting from v4.10can provide you a friendly environment to visualize BIOS update procedure. By the way, do not forget that target board MUST be AMIBIOS system while using this utility. FeaturesThis utility offers the following features:Small executable file sizeQuickly updateClear updating information and statusFully compatible with previous version (See Appendix B AFUWIN v3.xx Commands)RequirementsSupported Operating SystemAFUWIN Utility is supported in following operating system:Microsoft Windows 98Microsoft Windows MEMicrosoft Windows 2000Microsoft Windows NT 4.0Microsoft Windows XP/XP64Microsoft Windows PEMicrosoft Windows Vista 32/64Microsoft Windows PE 2.0 x64 (AFUWINx64.EXE)Microsoft Windows 7 32/64BIOS RequirementsSystem BIOS should have the followings:AMIBIOS CORE version 8.xx.xx.SMIFlash eModule with “8.00.00_SMIFlash-1.00.07” label or later.Token: SDSMGR_IN_RUNTIME = ON.Token: SMI_INTERFACE_FOR_SDSMGR_FUNC = ON.Operating System Driver RequirementsFollowing drivers for different operation system are required by this utility:UCOREVXD.VXD Driver for Microsoft Windows 98/MEUCORESYS.SYS Driver for Microsoft Windows NT/2000/XP/PEUCOREW64.SYS Driver for Microsoft Windows XP64 Getting Started InstallationCopies AFUWIN.EXE, AFUWINx64.EXE (for Microsoft Windows PE 2.0 x64), UCOREVXD.VXD, UCORESYS.SYS and UCOREW64.SYS to any storage location accessible by the host system and then run AFUWIN in command prompt. Remember that three files MUST be in same directory. For launching GUI mode, you can just double-click on the icon.UsageFor previous usage, see Appendix B AFUWIN v3.xx Commands to know details. AFUWIN [Option 1] [Option 2]……….OrAFUWINOrAFUWIN /MOrAFUWIN /MAIBIOS ROM File NameThe mandatory field is used to specify path/filename of the BIOS ROM filewith extension.CommandsThe mandatory field is used to select an operation mode:/O Save current ROM image to file/U Get and display ROM ID from ROM file/Ln Refer to option: /Ln/M Refer to option: /M/MAI Display current system and ROM file's MA/HOLE Update specific ROM hole by given name/HOLEOUT Save specific ROM holedata by given name/D Verification test of given ROM file withoutflashing/EC Flash EC firmware BIOS (Refer to OFBDspec)Path: $BIOS/Corebin/800/ROMUtils/On FlashBlock Description Specification.PDF.Sample Code Module Path:$BIOS/Examples/On Flash Block Description ?/NCB Flash NCB data by given name/NCBOUT Output NCB data by given name/C Destroy CMOS checksumOptionsThe optional field used to supply more information for flashing BIOS ROM.Following lists the supported optional parameters and format:?/P Program main bios image /B Program Boot Block/N Program NVRAM/C Destroy CMOS after update BIOS done/E Program Embedded Controller block if present /K Program all non-critical blocks/Kn Program n’th non-critical block only (n=0 – 7)/Q Quiet mode enable/REBOOT Reboot after update BIOS done/X Do not check ROM ID/S Display current system’s BIOS ROM ID/Ln Load CMOS default (n=0 - 1)L0: Load current CMOS optimal settingsL1: Load current CMOS failsafe settingsL2: Load CMOS optimal settings from ROMfileL3: Load CMOS failsafe settings from ROMfile/MUpdate BootBlock MAC address if exists/R Preserve all SMBIOS structures duringNVRAM programming/Rn Preserve specific SMBIOS structure duringNVRAM programming/ECUF Update EC BIOS when newer version isdetected./ShutDown Shutdown system after programming./clnevnlog Clean Event Log./DeDftCfg Delete all default settings from BIOS./-Command Name Delete certain command’s default setting.[OEM Uses Only.]/MEUF Update Intel ME ignition firmware./ME Update entire Intel ME region.(WinPE only)Note : Running AFUWIN under command prompt directly will display help message. ExamplesExamples on how to update BIOS using the command prompt are shown infollowing:Save current BIOS ROM to fileAFUWIN /OGet and display ROM ID from BIOS ROM fileAFUWIN /UUpdate main BIOS image onlyAFUWINOrAFUWIN /pUpdate Boot Block onlyAFUWIN /BUpdate NVRAM onlyAFUWIN /NUpdate Embedded Controller Block onlyAFUWIN /EUpdate Embedded Controller Block if newer version is detected AFUWIN /ECUFUpdate 2nd non-critical block onlyAFUWIN /K2Update main BIOS image, Boot Block and NVRAM at onceAFUWIN /P /B /NUpdate whole BIOS ROMAFUWIN /P /B /N /C /E /KUpdate whole BIOS ROM and load current CMOS optimal settings AFUWIN /P /B /N /C /E /K /L0 Update whole BIOS without checking ROM IDAFUWIN /P /B /N /C /E /K /XUpdate whole BIOS with quiet executionAFUWIN /P /B /N /C /E /K /QUpdate whole BIOS in quiet mode and REBOOT quietlyAFUWIN /P /B /N /C /E /K /Q /REBOOTUpdate BootBlock MAC addressAFUWIN /MUpdate whole BIOS and BootBlock MAC addressAFUWIN /P /B /N /C /E /K /M?Update whole BIOS except existing SMBIOS structuresAFUWIN /P /B /N /C /E /K /RUpdate whole BIOS but preserve SMBIOS type 0 and 11AFUWIN /P /B /N /C /E /K /R0 /R11Update dedicate ROM Hole AreaAFUWIN /Hole:NameUpdate dedicate NCB AreaAFUWIN /NCB:NameOutput dedicate ROM Hole FileAFUWIN /HOLEOUTt:NameOutput dedicate NCB FileAFUWIN /NCBOUT:NameCancel Embedded AFU default commands- Below sample cancels B & P commands if BIOS has embedded B & P commands in OFBD.AFUWIN /-B /-PNotice: if /p & /b are set as default command only and /-B /-P commands are issued then P command will still be issued because if none of command is issued then /p will still issue as AFU default.Cancel ALL Embedded AFU default commandsAFUWIN /DeDftCfgMain WindowButtonsClick this button to search for BIOS ROM file from any disk drive.Click this button to starting update BIOS.Click this button to save BIOS ROM image to disk drive.Click this button to exit this program.Function FrameInformation TabThis tab displays system BIOS information for your reference before flashingBIOS.FieldSetup TabThis tab allows you to change the settings for flashing BIOS.FieldFailsafe BIOS after flashing.Select to destroy CMOS checksum after flashing.Destroy CMOSThis is default setting in CMOS Option block.CheksumThis tab displays the updating status.FieldFunctionsTo launch into AFUWIN with GUI mode, you can double-click the executable file icon to open the operating window:Usually, system BIOS information will be displayed first, but you may see a pop-up dialog if the system does not support AMIBIOS update function. After open this program successfully, you can refer to following steps to finish the operation what you need: Saving system BIOS ROM image to file1.Press button to open file dialog box.2.Select path and input a file name.3.Click on OK button to save system BIOS ROM image into specific file.4.Press button to exit this program.Flashing system BIOS with given file1.Press button to search for BIOS ROM image file from any disk driver andload it into memory.2.Switch to Setup Tab to check and change necessary settings.3.Press button to start the operation.4.Progess Tab will be switched automatically and display the programming status.5.After BIOS updated, you can press button to exit this program or systemwill restart automatically if the Restart After Programming option enabled. Error Code ListAppendix B : AFUDOS v3.xx CommandsUsage : AFUDOS /i [/o] [/n] [/p[b][n][c][e]] [/s] [kN] [/c[N]] [/q] [/h] [/t] [/u[ROM File Name]]Following table lists the description of previous version of AFUDOS commands.。

联想消费笔记本产品促销培训

智能感光系统
－根据环境光线变化自动调节屏幕亮度－节能省电，保护眼睛
环境光
屏幕亮度
Lenovo Confidential
Presentation Title Goes Here | © 2008 Lenovo
Lenovo Confidential Lenovo Confidential Lenovo Confidential
配备LED背光高清屏，HDMI以及VGA端口，提供丰富的多媒体体验。内置3G模块*让您随时随地畅享高速上网，收发邮件，在线视频。
一键拯救，APS硬盘保护，ALS智能感光系统* 以及超长电池续航等，让您自由自在、舒适高效、放心使用！
丰富接口
网络互联
多媒体体验
人性化设计
超薄时尚设计
低功耗长续航
全功能PC
二级缓存 3M 3M 2M 2M 1M 1M
前端总线 1066Mhz 1066Mhz 800Mhz 800Mhz 800Mhz 800Mhz
TDP 25W 25W 35W 35W 35W 35W
注解性能提升约7％性能提升约10％性能提升约5％
（3）Y550内存/硬盘升级
－Y550全线升级双通道4G DDR极速内存－Y550全线升级500G超大硬盘
Page 10 of 8
Lenovo Confidential
Ideapad Y系列产品介绍 Ideapad U系列产品介绍
Ideapad S系列产品介绍 Lenovo G系列产品介绍
Lenovo Confidential
Presentation Title Goes Here | © 2008 Lenovo
Page 9 of 8
Lenovo Confidential

CM2009中文资料

PIN DESCRIPTIONS
DESCRIPTION This is an isolated supply input for the SYNC_1 and SYNC_2 level shifters and their associated ESD protection circuits. This is a supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection circuits. Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. Ground reference supply pin. This is an isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates.

ethernet-controller-i210-i211-faq

Intel® Ethernet Controller I210/I211 Frequently Asked QuestionsNetworking Division (ND)March 2016Revision 0.7Order Number: 334026-001Intel ® Ethernet Controller I210/I211 FAQs 2LegalNo license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a Particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications and roadmaps. The products and services described may contain defects or errors which may cause deviations from published specifications. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting /design/literature.htm . Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries. * Other names and brands may be claimed as the property of others. © 2016 Intel Corporation.Intel ® Ethernet Controller I210/I211 FAQs3Revision HistoryRevisionDate Notes 0.7March 2016 Updated sections 2.18 and 2.19. 0.6 August 5, 2014 FAQs added or updated:•- Why does the I210 not work after EEUPDATE successfully programs the image? (Updated) • 2.38 - I plan to use the I210 as an iSCSI interface or iSCSI boot device. The datasheet lists EEPROM word 0x1E bit 11 as iSCSI enable. Should I set that bit? (Added)0.5 May 2, 2014 Initial public release.Intel® Ethernet Controller I210/I211 FAQs Note: This page intentionally left blank.4Intel ® Ethernet Controller I210/I211 FAQs51 Summary (7)1.1Product Name ........................................................................................................ 7 1.2 Background .. (7)2 Technical and Design FAQ ................................................................................. 7 2.1 How do I find all the I210/I211 collateral? . (7)2.2 Can any magnetics, RJ-45, or Integrated Connector Module (ICM) be used with the I210/I211? (7)2.3 Where can I get a recommended Bill of Materials (BOM)? (7)2.4 What power supplies does the I210/I211 require? (8)2.5 Do the I210/I211 have start-up and shut-down power rail requirements? (8)2.6 Is the I210/I211 backward compatible with other Ethernet controllers? (8)2.7 Does Intel provide design review support? (8)2.8 Does I210-IS support backplane applications? (8)2.9 Does the I210/I211 support Non-Volatile Memory (NVM)-less (EEPROM-less) designs? (8)2.10 Does the I210 need to be reset after updating bits in the flash memory or upgrading to a completely new flash memory? (9)2.11 What speeds do the I210/I211 support? (9)2.12 Is Management Component Transport Protocol (MCTP) supported? (9)2.13 What are the PCI Device IDs for the I210/I211? (9)2.14 What file should I use to program the I210 or I211? (9)2.15 What tools do I use to program the I210/I211? (9)2.16 What NVM image should I select for the I210? (10)2.17 Does the Intel device driver support the 1588 protocol standard? (10)2.18 Do the I210 or I211 support pre-boot? (10)2.19 Where does the pre-boot (PXE, iSCSI, UEFI) Option ROM code reside? (10)2.20 Does the I210 and I211 support WoL? (10)2.21 Can the Subsystem PCI ID be changed in the I210/I211? (10)2.22 Does the I210 support 100Base-FX? (10)2.23 How does the security feature of the I210 work? (11)2.24 How does the security feature of the I211 work? (11)2.25 Why does the I210 not work after EEUPDATE successfully programs the image? (11)2.26 I am trying to setup AVB on my system. How can I do it? (11)2.27 Does the I210 support IPMI? (12)2.28 The layout guidelines describe the advantages of 85 Ω design vs. 100 Ω design for the differential traces (PCIe). But for SerDes, 100 Ω impedance is recommended. Are the same benefits not also valid for SerDes? (12)2.29 Is there a way to monitor the GMII interface (between MAC and PHY) on the I210? (12)2.30 Since SGMII is configurable, can the I210 be a MAC, and the other end a PHY, or vice versa? (12)2.31 What are the I210 SMBus slave addresses? (12)2.32 How do I interpret the chip markings on my I210 or I211? (12)2.33 Why is the Sample Validation Kit (SVK) not being updated? (12)2.34 Where do I find the latest software drivers for the I210 or I211? (13)2.35 Do the I210 and I211 support PCIe Spread Spectrum Clocking (SSC)? (13)2.36 Where can I get technical support? (13)2.37 Where can I find product briefs, datasheets, application notes, design guides, and other resources for developers? (13)2.38I plan to use the I210 as an iSCSI interface or iSCSI boot device. The datasheet lists EEPROM word 0x1E bit 11 as iSCSI enable. Should I set that bit? (13)Intel ® Ethernet Controller I210/I211 FAQs6 3 Sales and Marketing FAQ (14)3.1When did the Intel ® Ethernet Controller I210/I211 launch? .......................................... 14 3.2How can I purchase the Intel ® Ethernet Controller I210 or I211? ................................. 14 3.3What is the product name? ..................................................................................... 14 3.4Why did the naming convention change? .................................................................. 14 3.5Is there an EDK and Collateral List for the I210/I211? ................................................ 14 3.6What is the price of the I210/I211? ......................................................................... 14 3.7Does the I210/I211 support Energy Efficient Ethernet (EEE)? ...................................... 14 3.8Does the I210/I211 support any offloads? ................................................................ 15 3.9What virtualization technologies does the I210/I211 support? ..................................... 15 3.10What management interfaces are on the I210? ......................................................... 15 3.11What is the OS2BMC feature on the I210? (15)Intel ® Ethernet Controller I210/I211 FAQs1 Summary This document contains a list of Technical and Design Frequently Asked Questions (FAQs) and Sales and Marketing FAQs for the Intel ® Ethernet Controllers I210 and I211. It consolidates two separate FAQ lists into one. 1.1 Product Name•Intel ® Ethernet Controller I210 • Intel ® Ethernet Controller I211 1.2 BackgroundThe Intel ® Ethernet Controller I210 (I210) is a single port, compact, low power component that supports GbE designs. The I210-AT and IT offer a fully-integrated GbE Media Access Control (MAC) and a Physical Layer (PHY) port. The I210-IS offers a fully-integrated MAC and an SGMII/SerDes port that can be connected to a backplane or an external PHY. The I210 also supports PCI Express* [PCIe v2.1 (2.5 GT/s)].The Intel ® Ethernet Controller I211 (I211) is a single port, compact, low power component that supports GbE designs. The I211 offers a fully-integrated GbE MAC, PHY port, and supports PCI Express* [PCIe v2.1 (2.5 GT/s)]. Note that the I211 operates without an external flash memory.2.1 How do I find all the I210/I211 collateral?Some collateral is only available on Intel Business Link/ Intel Business Portal (IBL/IBP), which is protected under a Non-Disclosure Agreement (NDA). Other collateral is available to the general public. Contact your Intel Field Representative for access to NDA content. 2.2 Can any magnetics, RJ-45, or Integrated Connector Module (ICM) be used with the I210/I211?No. The magnetics module has a critical effect on overall IEEE and emissions conformance. The device should meet the performance required for a design with reasonable margin to allow for manufacturing variation. Occasionally, components that meet basic specifications can cause the system to fail IEEE testing because of interactions with other components or the Printed Circuit Board (PCB) itself. Carefully qualifying new magnetics modules prevents this problem. Refer to the latest Design Considerations section of the Intel ® Ethernet Controller I210/I211 Datasheets for a list of magnetics that have been qualified to work with the I210/I211. 2.3 Where can I get a recommended Bill of Materials (BOM)?The I210/I211 Datasheets list the recommended components to use with the I210/I211. The list contracts and expands over time, even after product launch, because some components reach end-of-life and new components are validated.72 Technical and Design FAQThe intended audience for this section is technical support and design engineers.Intel ® Ethernet Controller I210/I211 FAQs82.4 What power supplies does the I210/I211 require?The I210/I211 requires three power rails: 3.3 Vdc, 1.5 Vdc, and 0.9 Vdc. Intel recommends that board designers use the integrated switching voltage regulators derived from a single 3.3 Vdc supply to reduce BOM costs. A central power supply can provide the required voltage sources designed by a system power engineer. If the LAN wake capability is used, all voltages must remain present during system power down. External voltage regulators need to generate the proper voltage, supply current requirements (with adequate margin), and provide the proper power sequencing. Refer to the Power Supplies section in the I210/I211 Datasheets for additional information. 2.5 Do the I210/I211 have start-up and shut-down power rail requirements?Designs must comply with power sequencing requirements to avoid latch-up and forward-biased internal diodes. Refer to the I210/I211 Datasheets for more information. 2.6 Is the I210/I211 backward compatible with other Ethernet controllers?Intel makes every effort to keep things as simple as possible from a design migration perspective when providing a follow-on Ethernet controller, while providing our customers the richest feature set possible. The I210 adds Integrated Switching Voltage Regulators (iSVR), JTAG, NC-SI hardware arbitration, and four Software Definable Pins (SDPs) from previous Intel Ethernet controllers. The I211 adds Integrated Non-Volatile Memory (iNVM), an iSVR, and four SDPs. Due to this added functionality, exact pin compatibility with previous generations could not be maintained. The Intel ® Ethernet Controllers 82574/82583 to I210/I211 Design Guide explains what is required for a dual 82574/82583-to-I210/I211 design, but we do not recommend this option. 2.7 Does Intel provide design review support?Yes. The Intel Networking Division (ND) Platform Application Engineer (PAE) group can provide schematic and Computer Aided Design (CAD) layout support (the layout file needs to be in the Cadence file format). Submit your design review request through Intel Premier Support (IPS) against the I210/I211 product. Intel requires that the relevant checklist has been filled out by the design engineer and is submitted with the schematic and/or layout file (contact your Intel representative for access to the checklist). This enables many design errors to be caught very early in the design process, and greatly speeds up the turnaround time on the ND review. Once a PAE resource has been assigned the review, expect one week for schematic review feedback, and two weeks for layout review feedback. 2.8 Does I210-IS support backplane applications?Yes. The I210-IS has an interface that can support backplane applications. 2.9 Does the I210/I211 support Non-Volatile Memory (NVM)-less (EEPROM-less) designs?The I211 is designed to work without an attached flash memory.The I210 is designed to use an external flash memory, but can be used without one with very limited features. For example, no management interface or external PHY control via MDIO or I2C is available without flash memory.Intel ® Ethernet Controller I210/I211 FAQs92.10 Does the I210 need to be reset after updating bits in the flash memory or upgrading to a completely new flash memory? Firmware updates are now automatically followed by a firmware reset, which means the following flash memory words and section are the only ones requiring an AC power cycle:•Flash Device Size (FL_SIZE only) – word 0x11 • CSR Auto Configuration Power-Up LAN – module pointed by word 0x27If updating data in these sections, the power cord should be removed for ~20 seconds and a cold reboot needs to occur to reset the I210 and re-read the external flash memory contents into its internal registers. 2.11 What speeds do the I210/I211 support?The I210 and I211 support the following speeds:•1 GbE •100 Mb/s • 10 Mb/sAll three speeds are supported in copper and SGMII mode. SerDes modes only support GbE. 2.12 Is Management Component Transport Protocol (MCTP) supported?The I210 supports MCTP in the following combinations:•MCTP over SMBus/I2C Binding •MCTP over PCIe VDM Binding • NC-SI over MCTP2.13 What are the PCI Device IDs for the I210/I211?•I210-AT – 0x1531 (hardware default, indicating an unprogrammed device) •I211-AT – 0x1532 (hardware default, indicating an unprogrammed device) •I210-AT – 0x1533 •I210-IS/AS - 0x1536 SERDES Fiber •I210-IS/AS - 0x1537 SERDES Backplane (KX, BX) •I210-IS/AS - 0x1538 SGMII (external PHY controlled via MDIO or I2C) •I211-AT – 0x1539 •I210-IS/AS – 0x157C using iNVM (no flash memory) • I210-AT – 0x157B using iNVM (no flash memory) 2.14 What file should I use to program the I210 or I211?The image files are available on the Intel Business Link in document 513655. When programming the flash memory on an I210, you should always use the binary (.bin ) file. When programming the iNVM on an I210 or I211, you should use the appropriate text file. 2.15 What tools do I use to program the I210/I211?The tools for supporting these products are available on IBL in document number 348742. EEUPDATE is used to program the flash memory or iNVM in production environments. LANConf is designed for test and development purposes, but can also be used to program the flash memory or iNVM.Intel ® Ethernet Controller I210/I211 FAQs10 2.16 What NVM image should I select for the I210?The production images archive (document 513655) contains a list of images and their features. The SGMII image is intended for use with the I210-IS when interfacing with an external SGMII PHY and controlling it via the I 2C or MDIO interface. When connecting to an SGMII switch, use the appropriate KX image. 2.17 Does the Intel device driver support the 1588 protocol standard?Yes. The I210 supports IEEE 1588/802.1AS precision time synchronization. 2.18 Do the I210 or I211 support pre-boot?The I210 supports PXE, iSCSI boot, and UEFI. A SMASH-CLP agent expansion ROM is also available for instances where the iSCSI boot and PXE expansion ROMs are stored in the I210 local flash memory. The I211 (and the I210 when operating without a Flash) only supports PXE, only by storing the expansion ROM in system/BIOS flash memory, and only operating with default settings. 2.19 Where does the pre-boot (PXE, iSCSI, UEFI) Option ROM code reside?The available expansion ROMs can be stored in the local flash memory for NIC designs, or in the system/BIOS flash memory for LOM designs. When storing the expansion ROMs in the local flash memory, a minimum flash memory component size of 16 Mb is required.Also, note that PXE is only supported for the I211 (and the I210 when operating without a Flash) by storing the PXE code in the system BIOS flash memory.The tools for displaying and configuring the pre-boot firmware are available on in the archive Preboot.exe . The tools for BIOS developers to use to create images for inclusion in a BIOS are available in document 387754 on the Intel Business Link. 2.20 Does the I210 and I211 support WoL?Yes. However, the complete WoL solution is complex, and the system design engineer needs to assure all platform stack ingredients (BIOS, power delivery, software, NVM) interacting with the I210 or I211 are implemented correctly. 2.21 Can the Subsystem PCI ID be changed in the I210/I211?Yes. The device, subdevice, and subvendor ID’s can be changed. The device ID is a protected field and cannot be changed without loading a new signed image with a different ID. 2.22 Does the I210 support 100Base-FX?The I210 does not support 100BASE-FX natively. It is supported through SGMII with Intel’s software device driver. It requires an external PHY like the Marvell* 88E1112. The 88E112 could be embedded into an SFP module that supports 100BASE-FX.This solution could be:The I210 in SGMII mode <-> Marvell 88e112 <-> SFP cage.2.23How does the security feature of the I210 work?When the I210 is initializing, it checks for the presence of a flash memory component. If a flash memory component is present, it checks for a valid digital signature. If either of these conditions is false, the I210 reverts to the internal iNVM. If the internal iNVM is not programmed, the I210 assumes all hardware defaults, including a PCI ID of 0x1531. This may also happen if the flash memory is not ready at the time that the I210 initializes, so it is important that the flash memory component be powered from the same source as the I210.The NVM firmware images for the I210 are signed. Once the I210 successfully initializes with a signed firmware image, security is enforced (unless security is disabled by pulling down pin 12) and the image cannot be overwritten except a by a new signed image that has the same or higher security revision.Pin 12 on the I210 is designated for the purpose of overriding the security feature. To override the security when it is in effect, a pull down resistor can be applied to that pin. This pin is sampled during initialization to determine if security is disabled.Not all fields in the image are protected. Fields that are normally subject to change by the OEM, such as the MAC address, PCI subsystem ID fields and LED customizations, can be changed without invalidating the digital signature.The I210 can potentially be used without an external flash memory (with significant limitations) by using the iNVM instead. In that case, it operates the same as an I211. Refer to Section 2.24 for a description of the I211 security feature.2.24How does the security feature of the I211 work?The I211 has a lock-out mechanism after the iNVM is programmed to prevent any tampering/retry of the iNVM programming. It is activated by writing a special iNVM word auto-load structure, iNVM word address 0xA, bit 15 is set to 1b. The lock-out is active as long as the pin 12 (SECURITY-EN) strapping option is enabled (pulled up, not down). For details, refer to section 3.2 in the Intel® Ethernet Controller I211 Datasheet.2.25Why does the I210 not work after EEUPDATE successfullyprograms the image?When EEUPDATE stores the new image in an unprogrammed flash, it is not active until a power cycle forces the new image to be loaded into shadow RAM in the controller. Until a power cycle occurs, EEUPDATE functions like /verify, and /mac_dump will not work correctly. Once an I210 is programmed and running with a valid image, updates can be performed with only a system reboot with some exceptions (refer to section 2.10).2.26I am trying to setup AVB on my system. How can I do it?Intel provides the following resources to get AVB up and running on your system: •The I210 with AVB support included on a validation adapter (NIC) – limited availability•IEEE 802.1Qav Traffic shaper (w/SW extensions)•IEEE1588/802.1AS Precision Time Stamping•Time based transmission•Linux Reference Driver (IGB driver modified)•FreeBSD Reference Code (GPL free driver)•Intel® Ethernet Controller I210 [Springville]– Traffic Shaping and Time Synchronization Technical Brief – (Document ID:-496740 )This document describes the various features supported by the Intel I210 LAN controller to enable solutions to participate in time synchronization protocols and controls for transmission timing and scheduling within the Intel I210 LAN controller.Please consult these items and contact us if you need further support.The Ecosystem will need to provide:•Protocol Stack that formats the packets in the Media Protocol stack format (as defined per IEEE 802.1BA). This stack typically runs in user mode (this is the heavy lifting, and is thesecret sauce for vendors to generate revenue).•Application to take advantage of the protocol stack.2.27Does the I210 support IPMI?The I210 does not inherently support IPMI itself, but rather it supports the ability to send and receive Ethernet traffic that could be IPMI to and from a management controller. Since IPMI is such a common traffic type for a management controller, we have added specific filters to the I210 (and all other server controllers) to make filter configuration easier. However, the BMC could just as easily create filters for only FTP or HTTP traffic. We provide a highly-configurable filtering mechanism which the management controller can use to configure the type of Ethernet traffic it needs to receive, ranging from all traffic to only a specific type.2.28The layout guidelines describe the advantages of 85 Ω designvs. 100 Ω design for the differential traces (PCIe). But forSerDes, 100 Ω impedance is recommended. Are the samebenefits not also valid for SerDes?PCIe Gen1 is 100 Ω, PCIe Gen2 is 85 Ω, and SerDes is 100 Ω impedance ONLY. The I210 is recommended to use 85 Ω for PCIe signals.2.29Is there a way to monitor the GMII interface (between MACand PHY) on the I210?The GMII is not exposed in the I210.For external PHY use SerDes SKU and configure to use SGMII with SGMII capable PHY such as a Marvell 88e1112. Be advised, ND has not been able to interoperate with BRCM SGMII PHY so far. 2.30Since SGMII is configurable, can the I210 be a MAC, and theother end a PHY, or vice versa?In SGMII mode, the I210 is always a MAC and is never an SGMII PHY.2.31What are the I210 SMBus slave addresses?The SMBus slave address is configured in the NVM. The 7-bit address in the images supplied by Intel is 0x49.For additional details, refer to the NVM settings in Section 6.7.3.4, “SMBus Slave Addresses — Offset 0x03” in the Intel® Ethernet Controller I210 Datasheet.2.32How do I interpret the chip markings on my I210 or I211? Refer to the “Marking Diagram” section in the associated Specification Update document.2.33Why is the Sample Validation Kit (SVK) not being updated?When Intel ND products are production-ready, the SVK ingredients are delivered to different customer downloadable locations, thus the SVK process terminates. The software tools and NVM imagescontinue to be available on IBL/IBP as separate deliverables and the software drivers are available to the public at the Intel Download center.2.34Where do I find the latest software drivers for the I210 orI211?Intel Download center. The software drivers linked from this page are generic versions, and can be used for general purposes. However, OEMs might have altered the features, incorporated customizations, or made other changes to the software or software packaging they provide. To avoid any potential installation incompatibilities on your OEM system, Intel recommends that you check with your OEM and use the software provided via your system manufacturer. Intel or the OEM might not provide technical support for some or all issues that could arise from the usage of this generic version of software drivers.2.35Do the I210 and I211 support PCIe Spread Spectrum Clocking(SSC)?Yes. Both devices support PCIe SSC.2.36Where can I get technical support?Technical support is provided by the computer vendor. You can use the following links for Intel® Desktop Board and Intel® Server Board to find support information:•Intel® Desktop Board support•Intel® Server Board supportIntel develops network components used in motherboards and network adapters sold by OEMs such as Dell*, HP*, Gateway*, and IBM*. Network controllers that are built into the motherboard or network adapters sold by an OEM are supported by the OEM. Intel does not provide support for OEM integrated network controllers or OEM adapters.2.37Where can I find product briefs, datasheets, application notes,design guides, and other resources for developers?You can use the following link for product information on Intel® Ethernet Controllers: •Product information on Intel® Ethernet ControllersIntel offers a complete line of industry-leading, single- and multi-port 10 GbE, 1 GbE, and fast Ethernet LAN controllers with integrated MAC and PHY, providing high performance, low power consumption, and a smaller footprint. Offering 10 GbE, 1 GbE, and 100 Mb/s LAN controllers, PCIe, PCI, PCI-X, or LCI bus interfaces, in 16-, 32- or 64-bit architectures, Intel produces Ethernet LAN controllers that enable faster, smaller, and simpler designs.2.38I plan to use the I210 as an iSCSI interface or iSCSI bootdevice. The datasheet lists EEPROM word 0x1E bit 11 as iSCSIenable. Should I set that bit?No. The class code should be left as LAN controller (word 0x1E bit 11 = 0b). The iSCSI boot firmware and / or the iSCSI software client will emulate an iSCSI host bus adapter and provide the necessary support.Note that the following FAQ entries are not listed in any particular order or priority.3.1 When did the Intel ® Ethernet Controller I210/I211 launch? The I210/I211 products launched in November 2012.3.2 How can I purchase the Intel ® Ethernet Controller I210 or I211? Orders should be placed with an Intel ® Authorized Distributor or through your Intel contact.Ordering information can be found in the Intel ® Ethernet Controller I210/I211 Specification Update .3.3 What is the product name?The products are marketed as:•Intel ® Ethernet Controller I210 Family • Intel ® Ethernet Controller I211-AT.Note that 1 GbE wording is not used in the product name since the Roman numeral “I” already denotes the 1 GbE speed. 3.4 Why did the naming convention change?The Intel ® Ethernet Controllers I210/I211 follow the new product naming convention that ND products are using going forward. The new naming convention makes it easier to tell what type of product it is. The “I” is the Roman numeral for 1 denoting 1 GbE speed. Likewise, if the first letter is a Roman numeral “X”, it is a 10 GbE product. The next number is the series and then the version of the product. The I210/I211 are the follow-on product and feature set in the 200 series of products. The Intel ® 82574 and 82583 1 GbE Ethernet Controllers use the old naming. 3.5 Is there an EDK and Collateral List for the I210/I211?Yes, the link to the collateral list is:Networking and Comms Ethernet: Intel® Ethernet Controller I210_I211 (Springville_Pearsonville)The EDK is at:Ethernet: Gigabit Ethernet Controller .3.6 What is the price of the I210/I211?Please contact your authorized Intel distributor for pricing for the Intel ® Ethernet Controller I210 Family and Intel ® Ethernet Controller I211-AT. 3.7 Does the I210/I211 support Energy Efficient Ethernet (EEE)? Yes.3 Sales and Marketing FAQThe intended audience for this section sales, marketing, and management.。

TSB82AA2中文资料

ቤተ መጻሕፍቲ ባይዱ
元器件交易网
Contents
Section 1 Title Page 1−1 1−1 1−2 1−3 1−3 1−3 1−3 2−1 3−1 3−3 3−4 3−4 3−5 3−6 3−7 3−7 3−8 3−8 3−9 3−10 3−11 3−12 3−12 3−13 3−13 3−14 3−14 3−15 3−16 3−16 3−17 3−18 3−19 3−21 3−22 4−1 4−4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 TSB82AA2 Data Manual Document History . . . . . . . . . . . . . . . . . . . . . Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSB82AA2 Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 3.8 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 OHCI Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 TI Extension Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 CardBus Cis Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 CardBus CIS Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 Power Management Capabilities Pointer Register . . . . . . . . . . . . . . . 3.15 Interrupt Line and Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16 MIN_GNT and MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.17 OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.18 Capability ID and Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . 3.19 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 3.20 Power Management Control and Status Register . . . . . . . . . . . . . . . . 3.21 Power Management Extension Register . . . . . . . . . . . . . . . . . . . . . . . . 3.22 Multifunction Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.23 Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3.24 Link Enhancement Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.25 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.26 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Guide,

Applications
Computers Microprocessors Embedded Systems - appliances, automobiles Special purpose - military chips, high performance computing
ECE280 Digital Design Laboratory August 31, 2006
In1 In2
What is Digital Systems Design ?
• Digital Systems Design is a process that entails a systematic development of an idea into an architecture that can be implemented digitally.
• Available from /ise/logic_design_prod/webpack.htm
ECE280 Digital Design Laboratory August 31, 2006
What is a Digital System?
• A collection of interconnected digital modules designeபைடு நூலகம் to perform a particular service or function
Digital Systems
• High Level Digital Modules – Microprocessors/Microcontrollers – PLDs – ASICs • Low Level Digital Modules – Gates - AND, OR, NOR, etc. – Blocks - Adder, subtractor, shifter, etc.

TDA8954

Mono bridge-tied load configuration
THD + N = 10 %; RL = 4 Ω; VDD = 41 V; VSS = −41 V
THD + N = 10 %; RL = 4 Ω; VDD = 35 V; VSS = −35 V
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210 -
W
-
150 -
TDA8954TH
HSOP24 plastic, heatsink small outline package; 24 leads; low stand-off height
SOT566-3
TDA8954_1
Product data sheet
Rev. 01 — 24 December 2009
© NXP B.V. 2009. All rights reserved.
2 of 46
NXP Semiconductors
6. Block diagram
TDA8954
2 × 210 W class-D power amplifier
VDDA DIAG1
STABI PROT
VDDP2
VDDP1
IN1M IN1P
OSCREF OSC
MODE SGND
IN2P IN2M
3 (20) 10 (4)
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output power
Tj = 85 °C; LLC = 22 μH; CLC = 680 nF (see
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UC-2100-W Series Quick Installation Guide

P/N: 1802021000214 *1802021000214*UC-2100-W Series Quick Installation GuideVersion 3.2, January 2021Technical Support Contact Information/support2021 Moxa Inc. All rights reserved.OverviewThe UC-2100-W Series computing platform is designed for embedded data acquisition and processing applications. The computer comes with up to two software-selectable RS-232/422/485 full-signal serial ports and single or dual Ethernet LAN ports. In addition, the Arm-based computing platform is available in various models that can fulfill diverse interface requirements, such as dual serial, LAN ports, and wireless connections. These versatile communication capabilities let users efficiently adapt the palm-sized computing platform to a variety of complex communications solutions.Model Names and Package ChecklistThe UC-2100-W Series includes the following models:•UC-2114-T-LX•UC-2116-T-LXBefore installing a UC-2100-W computer, verify that the package contains the following items:•UC-2100-W Series computer•Console cable•Power jack•Quick Installation Guide (printed)•Warranty cardNotify your sales representative if any of the above items are missing or damaged.NOTE The console cable and power jack can be found inside the product box, beneath the molded-pulp cushion.Appearance UC-2114UC-2116LED IndicatorsThe function of each LED is described in the table below: LED Name Status FunctionPower Green Power is on, and the device isfunctioning normallyOff Power is offEthernet (10/100 Mbps) Green Steady On: 10 Mbps Ethernet linkBlinking: Data transmission is inprogressYellow Steady On: 100 Mbps Ethernet linkBlinking: Data transmission is inprogressOff Speed lower than 10 Mbps or thecable is not connectedEthernet (10/100/100 0 Mbps) Green Steady On: 100 Mbps Ethernet linkBlinking: Data transmission is inprogressYellow Steady On: 1000 Mbps Ethernet linkBlinking: Data transmission is inprogressOff Speed lower than 10 Mbps or thecable is not connectedSerial (Tx) Green Serial port is transmitting dataOff Serial port is not transmitting data Serial (Rx) Yellow Serial port is receiving dataOff Serial port is not receiving data User Green User ProgrammableLEDs that indicate the Wireless signal strength Yellow The number of glowing LEDsindicates the signal strength3 LEDs: Excellent2 LEDs : Good1 LED : PoorOff Wireless module is not detectedCAN1/CAN2 (Tx) Green CAN port is transmitting data Off CAN port is not transmitting dataCAN1/CAN2 (Rx) Green CAN port is receiving data Off CAN port is not receiving dataReset ButtonThe UC-2100-W Series computer is provided with a reset button, which is located on the top panel of the computer. To reboot the computer, press the reset button less than 1 second. Press and hold the reset button between 7 to 9 seconds to reset the computer to the factory default settings. When the reset button is held down, the User LED will blink twice every second. The User LED will become steady when you hold the button continuously for 7 to 9 seconds. Release the button within this period to load the factory default settings.Installing the ComputerWall or Cabinet MountingUse two screws per side to mount the UC-2100-W Series on a wall or inside a cabinet.Wiring RequirementsBe sure to read and follow these common safety precautions before proceeding with the installation of any electronic device:•Use separate paths to route wiring for power and devices. If power wiring and device wiring paths must cross, make sure the wires are perpendicular at the intersection point.NOTE Do not run signal or communication wiring and power wiring in the same wire conduit. To avoid interference, wires with differentsignal characteristics should be routed separately.•Use the type of signal transmitted through a wire to determine which wires should be kept separate. The rule of thumb is that wiring that shares similar electrical characteristics can be bundled together. •Keep input wiring and output wiring separate.•It is strongly advised that you label wiring to all devices for easyidentification.CAUTIONBe careful when handling the unit. When the unit is plugged in, the internal components generate heat, and consequently the outer casing may feel hot to the touch.Connecting the PowerConnect the 9 to 48 VDC power line to the terminal block, which is connected to the UC-2100-W Series computer. If the power is supplied properly, the “Power” LED will glow a solid green light. The power input location and pin definition are shown in the adjacent diagram. The input terminal block (CN5) is suitable for a wire size of 12 to 30 AWG (3.3 to 0.05 mm 2) and a torque value of 0.5 N-m (4.425 lb-in).Grounding the UnitGrounding and wire routing help limit the effects of noise due toelectromagnetic interference (EMI). Run the ground connection from the terminal block connector to the grounding surface prior to connecting the power. Please note that this product is intended to be mounted on a well-grounded mounting surface, such as a metal panel. The minimum cross-sectional area of the earthing conductor shall be equal to the input wiring cable.Connecting to the Console PortThe UC-2100-W console port is a 4-pin pin-header RS-232 port located on the right panel of the case. It is designed for serial console terminals, which are useful for viewing the boot up message, or for debugging system boot up issues. Remove the protective cover on the port to connect the console cable.Serial Console Port & PinoutsSerial Console CablePin Signal 1 TxD 2 RxD 3 NC 4GNDConnecting to the NetworkThe Ethernet ports are located on the top or bottom panel of theUC-2100-W computers. The pin assignments for the Ethernet port are shown in the following figure. If you are using your own cable, make sure that the pin assignments on the Ethernet cable connector match the pin assignments on the Ethernet port.Pin 10/100 Mbps10/100/1000 Mbps1 Tx+ TRD(0)+2 Tx- TRD(0)-3 Rx+ TRD(1)+4 – TRD(2)+5 – TRD(2)-6 Rx- TRD(1)-7 – TRD(3)+ 8–TRD(3)-Connecting to a Serial DeviceThe serial ports are located on the bottom panel of the UC-2100-W computer. Use a serial cable to connect your serial device to the computer’s serial port. These serial ports have male DB9 connectors and can be configured for RS-232, RS-422, or RS-485 communication. The pin location and assignments are shown in the following table.PinRS-232 RS-422 RS-485 (4-wire) RS-485 (2-wire)1 DCD TxDA(-) TxDA(-) –2 RxD TxDB(+) TxDB(+)–3TxD RxDB(+) RxDB(+) DataB(+) 4 DTR RxDA(-) RxDA(-) DataA(-) 5 GND GND GND GND 6 DSR – – – 7 RTS – – – 8CTS–––Connecting to a CAN DeviceThe UC-2114 and UC-2116 come with two CAN ports, which use the 5-pin terminal block and are compatible with the CAN 2.0A/B standard. The pin assignment of the port is shown below.Pin Signal 1 GND 2 L 3 Chassis4 H 5VoutInstalling SIM CardsYou will need to install a SIM card on your UC-2100-W computer. Follow these steps to install the SIM card.1.Remove the screw on the cover locatedon the right panel.2.Insert the SIM card into the socket. Makesure you place the chip-side on thebottom.3.To remove the SIM card, simply push theSIM card and release it.Installing the microSD CardBoth UC-2114 and UC-2116 come with a storage socket that allows users to install one microSD card. Follow these steps to install the microSD card:1.The microSD socket is located below theright panel of the computer. Unfasten thescrew and remove the right panel cover.2.Insert the microSD card into the socket.Ensure that the card is inserted in theright direction.3.Replace the cover and fasten the screwon the cover to secure the cover.To remove the microSD card, simply push the card in and release it. Adjusting the DIP SwitchThe UC-2114 and UC-2116 computers come with one DIP switch for users to adjust the serial port parameters. To set up the DIP switch, do the following:1.Remove the screws on the DIP switch coverlocated on the rear panel of the computer.2.Remove the thin film on the DIP switch andadjust the setting as required.Refer to the table below for the DIP switchsettings. The default value is OFF.SW1 2 34 Low High Term. –ON 1 KΩ 1 KΩ120 Ω– OFF 150 KΩ150 KΩ– –Real-time ClockThe real-time clock in the UC-2100-W is powered by a lithium battery. We strongly recommend that you do not replace the lithium battery without the help of a Moxa support engineer. If you need to change the battery, contact the Moxa RMA service team.Accessing the UC-2100-W Using a PCYou can use a PC to access the UC-2100-W by one of the following methods:A.Through the serial console port with the following settings: Baudrate= 115200 bps, Parity = None, Data bits = 8, Stop bits = 1, Flow Control = None.ing SSH over the network.Refer to the following IP addresses and login information:Default IP Address Netmask LAN 1 192.168.3.127 255.255.255.0LAN 2 192.168.4.127 255.255.255.0Login: moxaPassword: moxaATEX and C1D2 Specifications ModelUC-2114-T-LX, UC-2116-T-LXRating Input: 9 to 48 VDC; 0.6 to 0.12 AATEX InformationII 3 GCertificate Number: DEMKO 19 ATEX 2297XCertification String: Ex nA IIC T4 GcAmbient Range: -40°C ≦Tamb ≦75°CRated Cable Temp ≧90°CC1D2 Information Temperature Code (T-code): T4 Manufacturer’sAddressNo. 1111, Heping Rd., Bade Dist., Taoyuan City334004, TaiwanHazardous LocationCertificationEN 60079-0:2012+A11:2013/IEC60079-0:2011 Ed. 6EN 60079-15:2010/IEC 60079-15:2010 Ed. 4。

73S1210F Evaluation Board Quick Start 说明书

73S1210F Evaluation Board QS_1210F_009 August 2009 Rev. 1.1© 2009 Teridian Semiconductor Corporation 1IntroductionThe 73S1210F Evaluation Board is a turnkey serial smart card reader development kit for the efficient evaluation and development of stand-alone solutions. The board provides two card interfaces. The board can be used in conjunction with any Windows ® XP host system that has an RS-232 port. The host application can access the board through the Teridian Pseudo-CCID (PCCID) commands to communicate with asynchronous smart cards, following T-0 and T-1 protocols, in compliance with ISO7816-3 and EMV4.1 standards.For details about use of this development board in embedded applications (i.e. platforms other than PC Windows XP), refer to the 73S12xxF Pseudo-CCID Host Application Guide (UG_12xxF_052) or contact Teridian support.System Requirements•A PC running Microsoft ® Windows XP and equipped with a serial port. •Eight megabytes of disk storage for the Teridian Exerciser application and documentation.Package Contents•A 73S1217F/1210F Evaluation Board populated with a 73S1210F and pre-loaded with the Teridian Pseudo-CCID firmware. •A CD containing the Exerciser application generic host driver and documents. •RS-232 Serial cable, Female/Male, 2 meters. •A 5V DC power supply.Default SetupThe 73S1210F Evaluation Board ships with a default configuration suitable for use as a turnkeyTransparent Smart Card Reader using a Pseudo-CCID over serial connection to communicate with a host PC application. The board’s hardware and firmware are pre-configured by Teridian to work in this state and the information in this document assumes this default configuration. Refer to the 73S1210Evaluation Board User Guide (UG_1217F_035) for details on alternate hardware configurations and uses.Software Installation on Windows XPFollow these steps using a PC running Windows XP:• Extract “PCCID V y.yy Release.zip” (where y.yyis the latest version of the firmware release). o Create an install directory. For example: “C:\TSC\”.o Unzip “PCCID V y.yy Release.zip” to the just created folder. All applications and documentation needed to run the board with a Windows PC will be loaded to this folder.• Connect the Serial cable between the host system and the board.• Plug the supplied adapter into the 5V DC jack on the board.Press the ON/OFF button once. The power LED D8 should turn on.• At this point the application is now installed and the development board is ready to use. The provided host application or any other host application can now be launched from Windows XP to access the smart card reader.THIS EVALUATION SYSTEM IS ESD SENSITIVE! ESD PRECAUTIONS SHOULD BETAKEN WHEN HANDLING THE BOARD!73S1210F Evaluation Board Quick Start Guide QS_1210F_009Demonstration Host ApplicationIncluded on the CD is a demonstration application named “TSCP-CCID.exe” which is located in the“x:\yyy\ \PCCID V z.zz Release\Host Applications\Windows App\App\Bin\Release” directory (where x refers to the drive, yyy refers to the directory the installation .zip file was expanded to and z.zz is the latest version of the firmware release). This is a host application that allows:•Smart card activation and deactivation, in ISO or EMV mode.•Smart card APDU commands to be exchanged with the smart card inserted in the board.•Starting a test sequence in order to test and evaluate the board performance against an EMV test environment.Run TSCP-CCID.exe to execute the host demonstration application. At this point the application window should appear. For additional information regarding the use of the Teridian Host application, refer to the Pseudo-CCID Host GUI Users Guide (UG_12xxF_037).Integration in an Embedded SystemThe 73S1210F Evaluation Board can also be connected to a host microprocessor in an embedded architecture, like in Point-of-Sales terminals, solid-state utility meters and digital Set-Top Boxes. In such cases, a software Pseudo-CCID driver must be integrated within the host processor embedded software. The Teridian CD provided with this Development Board includes the ANSI C source code of the Teridian generic driver that will allow seamless integration into virtually and processor and operating system. For additional information, refer to the 73S12xxF Pseudo-CCID Host Application Guide (UG_12xxF_052).© 2009 Teridian Semiconductor Corporation. All rights reserved.Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.Microsoft and Windows are registered trademarks of Microsoft Corporation.All other trademarks are the property of their respective owners.2 Rev. 1.1。

65nm_Signoff

65nm_SignoffProprietary & Confidential C65nm Signoff2009 TSMC, Ltd Design and Technology Platform2009 TSMC, Ltd.Contentsz Signal EM Flow z Power Grid Sign-off z Timing Closure & Sign-off z Dummy filling flow & Timing fixing z Others Proprietary & Confidential C2009 TSMC, LtdDTP/ P. 22009 TSMC, Ltd.Signal EM Analysisz Peak/Avg./RMS current z AstroRail or TSMC utility (Ref. Flow 4.0/5.0)Proprietary & Confidential C2009 TSMC, LtdDTP/ P. 32009 TSMC, Ltd.Proprietary & Confidential CSignal EM Analysis Procedure1. The temperature for the signal EM analysis: 125C.2. The RC corner for the RC extraction: Cworst in 125C.3. The power consumption is calculated in the LT corner, or the ML corner.4. Set the reasonable switching activity in the signal EM analysis.2009 TSMC, LtdDTP/ P. 42009 TSMC, Ltd.Power Integrityz Power grid signed-off in three modesProprietary & Confidential CStatic IR dropAverage power IR drop < 5% VDD+VSS (wire-bond) 3% ( Flip chip)Dynamic IR drop4-5X Static IR < 15% VDD + VSS ? Dcap insertionScan Peak IR around clock-edge < 30% VDDPeak power usually around clock-edge ? Seen many chips failing even in scan-mode ? Analyzing IR drop during small timing window when flops are switchingz Power reductions2009 TSMC, LtdLeakage: Multi-Vt by default Dynamic: RTL clock gating is highly recommended Comprehensive power approaches for portable deviceDTP/ P. 52009 TSMC, Ltd.Proprietary & Confidential CPower Integrity Procedure1. The temperature for the power EM analysis: 125C.2. The RC corner for the RC extraction: CWorst in 125C.3. The power consumption is calculated in the LT corner, -40C/110% VDD/FF, or the ML corner.4. Set the reasonable toggle rate to calculate the average power consumption.5. The EM spec is tight in 125C, the current is large in the LT or ML corner, and the power EM criterion in such condition should be most robust.2009 TSMC, LtdDTP/ P. 62009 TSMC, Ltd.Scan Peak PowerProprietary & Confidential Cz The most of flops are switching at almost the same Current time CLK Many flops switching Timing window (t)2009 TSMC, LtdClock skew + Average CK-Q delay + Average Transition/2DTP/ P. 72009 TSMC, Ltd.Scan Power AnalysisATPG Test Patterns Peak Switching Cycle Search IR Sensitivity of Each Flop Flop Transition at Peak Switching CycleProprietary & Confidential CPeak Power CalculationSDF & SDCDynamic IR AnalysisPeak IR Report & Hot Spot Colormap2009 TSMC, LtdDTP/ P. 82009 TSMC, Ltd.Static vs. Dynamic IR-dropProprietary & Confidential CCurrent envelope Average currentPeak currentnT(n+1)T(n+2)TWire sizing can be used to control static IR-drop Critical de-cap provides immediate spike filtering2009 TSMC, LtdDTP/ P. 92009 TSMC, Ltd.65nm PI sign off criteriaTechnology node: 65nm PI sign off criteria recommendedPackage Wirebond w/o pkg Static 5% w/ pkg 5% w/o pkg 3% Flipchip w/ pkg 3%Proprietary & Confidential CCornerFF/SS VDD: TT FF/SS VDD: TT FF/SS VDD: TT FF, TT VDD: TT FF, TT VDD: TTVCD Function Vectorless Dynamic VCD Scan Vectorless10%15-18%8-10%13-15%10%15-18%8-10%13-15%10%15-18%8-10%13-15%10%15-18%15-18%13-15%2009 TSMC, LtdIR limit : VDD+GNDDTP/ P. 102009 TSMC, Ltd.Timing Closure(By customer with 10% (By customer with 10% setup time margin && setup time margin CWLM) CWLM)Proprietary & Confidential CSynthesis Synthesis(Double width ++ spacing (Double width spacing ++ via) via) CTS/CTO CTS/CTOSignal SignalEM EM Fixing Fixing Decap Decap Insertion Insertion Double DoubleVia ViaTD TDPlacement Placement(Netlist w/ hold aware (Netlist w/ hold aware buffer insertion +setup buffer insertion +setup time driven) time driven) (Decap pre-insert, Xtalk (Decap pre-insert, Xtalk prevention, Ant. fixing) prevention, Ant. fixing)Detail Detailrouting routing(Derive setup time (Derive setup time requirement for ICG) requirement for ICG)Trial TrialCTS CTSRC RCExtraction Extraction Setup/Hold Setup/Hold fixing fixing(setup/hold fixing) (setup/hold fixing)Setup Setuptime timeOpt. Opt.Dummy DummyFill Fill(setup/hold fixing) (setup/hold fixing)(All sign-off modes) (All sign-off modes)Power PowerOpt. Opt.(Multi-Vt swap) (Multi-Vt swap)2009 TSMC, Ltd(Glitch && setup/hold (Glitch setup/hold fixing) fixing)Xtalk XtalkFixing FixingSTA STASign-off Sign-offDTP/ P. 112009 TSMC, Ltd.Proprietary & Confidential CTiming Sign-offz Timing closure taking all kinds of following effects into accountMulti-mode STA ? Multiple Device & RC CornersWC, WCL, BC or LT (-40C) ? Cworst, Cbest (RCworst, RCbest, RCtypical)OCV, Hold margin ? Crosstalk ? DFM –Dummy metals, Dummy Vias2009 TSMC, LtdDTP/ P. 122009 TSMC, Ltd.Proprietary & Confidential COCVz OCV – On Chip Variation2009 TSMC, LtdDTP/ P. 132009 TSMC, Ltd.Proprietary & Confidential CTiming Sign-off Recommendationz Clock jitter is not includedWC + Cworst 65nm Setup/ hold WCL + Cworst Setup/ hold BC or LT + Cbest/Cworst hold Max. transition 0.6ns* Setup margin 0 Hold margin 50psOCV WC: 5% BC:10%*Max transition applied at WC corner. *Over constraint is recommended at APR stage. **Typical number showed here: - OCV and Hold margin design dependant: transition, cell types, IR-drop **Corner shown here: - It is the basis. Customer should add more corners based on product application. ? 2009 TSMC, LtdDTP/ P. 142009 TSMC, Ltd.Proprietary & Confidential CDummy filling flow & Timing FixingAPR APRAdd Exclusive layer Add Exclusive layer at clock nets at clock netsRC RCextraction extractionSTA STAGDS Timing violationsCalibre CalibreDummy GDS2009 TSMC, LtdECO ECODTP/ P. 152009 TSMC, Ltd.(Fi iProprietary & Confidential CDummy Fill Guidelinesz In a cell-based design area, it’s recommended to use fi ller cell with DPO/DOD for empty area (please refer TSMC N90 standard cell library). z It’s recommended to use TSMC fill utility for macro block and chip top level for final GDSII to guarantee global uniformity. z If using TSMC fill utility for DM and DOD, low densities violations could be waived by TSMC PE. Otherwise, all densities rules should be met. z Do dummy fill in a bottom-up approach.Macro block meet rules and timing first, then chip level.2009 TSMC, LtdDTP/ P. 162009 TSMC, Ltd.Macro IP Dummy Fill Timing FlowN90 Dummy Mx utility DMx GDSII GDS Merge N90 Dummy PO,OD utility DPO, DOD GDSII Dummy GDSIIProprietary & Confidential CMake dummy top cell name the same as IP top cell for StarRC-XTOriginal IP GDSII Milkyway Database LVS/LPE by Hercules LPE Netlist (device) RCX by Star-RCXT RCX Netlist (device+RC) GDS MergeFinal IP GDSIIPost-layout Simulation*mky.gds.map OD 6 1 poly 17 1 metal1 31 1 metal2 32 1 … metal1 31 7 metal2 32 7 …* Star-RCXT command file METAL_FILL_GDS_FILE: dummy.gds GDS_LAYER_MAP_FILE: mky.gds.map METAL_FILL_POLYGON_HANDLING: FLOAT2009 TSMC, LtdDTP/ P. 172009 TSMC, Ltd.Top (Digital) Dummy Fill Timing FlowN90 Dummy Mx utility Chip GDSII N90 Dummy PO,OD utility DPO, DOD GDSII DMx GDSII GDS Merge Dummy GDSII Proprietary & Confidential CMake dummy top cell name the same as chip top cell for StarRC-XTGDS MergeFinal chip GDSIIP&R Milkyway DatabaseRCX by Star-RCXTSPEF w/ dummy impactSign-off STA*mky.gds.mapECO* Star-RCXT command file METAL_FILL_GDS_FILE: dummy.gds GDS_LAYER_MAP_FILE: mky.gds.map METAL_FILL_POLYGON_HANDLING: FLOAT2009 TSMC, LtdOD 6 1 poly 17 1 metal1 31 1 metal2 32 1 … metal1 31 7 metal2 32 7 …DTP/ P. 182009 TSMC, Ltd.Others: High-Speed ClocksTop-viewM3/M5Proprietary & Confidential CM4M2/M4End-viewClock netClock NetVIA34M3M32009 TSMC, LtdDTP/ P. 192009 TSMC, Ltd.Shielding Net。

tps54040

Under voltage lockout is internally set at 2.5V, but can be increased using the enable pin. The output voltage startup ramp is controlled by the slow start pin that can also be configured for sequencing/tracking. An open drain power good signal indicates the output is within 93% to 107% of its nominal voltage.
Skipping Eco-Mode™ • 116µA Operating Quiescent Current • 1.3µA Shutdown Current • 100kHz to 2.5MHz Switching Frequency • Synchronizes to External Clock • Adjustable Slow Start/Sequencing • UV and OV Power Good Output • Adjustable UVLO Voltage and Hysteresis
• 0.8-V Internal Voltage Reference • MSOP10 Package With PowerPAD™ • Supported by SwitcherPro™ Software Tool
(/docs/toolsw/folders/print/s witcherpro.html)
1 500 –40 to 150 –65 to 150
UNIT
V

952ss00Intro2

ShoushuiWei © 2009 SDUBME-SS0-Intro-7
Signal Frequency Characteristics:
f (Hz) 10 20K 100M 300M 40G 2.4G 300G
Voice Signals
Communication Satellite
Microwave Link
Introduction
ShoushuiWei © 2009 SDUBME-SS0-Intro-11
Examples of Signals & Systems:
Circuit
• Voltages & currents
Automobile
• Pressure on accelerator & automobile speed
Fall 2009
Signals and Systems
Chapter SS-0 Introduction
ShouShui Wei
SDU-BME Sep08 - Dec08
Figures and images used in these lecture notes are adopted from “Signals & Systems” by Alan V. Oppenheim and Alan S. Willsky, 1997
Course Flowchart in SDU-BME
ShoushuiWei © 2009 SDUBME-SS0-Intro-2
Study Electronics
Circuit Study
Differential Equations
Linear equations

方正睿逸R500内部培训材料

5450
7499
Intel C2Q Q8200 （酷睿2四核心，45nm，主频2.33GHz
BSN300-875A
，4M共享二级缓存）/ 4G DDRII / 500G SATA / Nvidia Quadro FX570 256M专业高性能图形显卡 / 集成千兆网卡 / DVDRW / 光电鼠标 / Windows Vista Basic中文版
目录
一、产品介绍二、功能亮点介绍
存储共享简单易用安全保护
三、产品功能总结四、产品部署拓扑
存储共享
Storage & Share
功能亮点介绍---存储共享
大容量共享存储
睿逸R500存储服务器，为用户提供了一个共享平台，省去了来回拿移动硬盘拷文件的繁琐，而且还省去了零散的众多副本文件，实现了集中存储，提高了存储有效率，大家可以共享睿逸R500上的文件资料。
方正睿逸R500内部培训材料
一、近期动态
第二届国际D2B峰会暨清华国际设计管理大会
演示用机及唯一参展PC产品
★国际顶尖设计大师联袂出席 ★国际设计管理界认可的权威奖项 ★全球近百家设计相关企业、高校共同参加 ★国际设计界与中国企业界的交流
一、价格
设备型号
配置
显示器
整机代整机媒理价体价
BSN30-655A
Intel PDC E5200（酷睿2架构，双核心，45nm，主频 2.5GHz，2M共享二级缓存）/ 2G DDRII / 320G SATA2 / Nvidia Quadro FX570 256M专业高性能图形显卡 / 集成 19〞宽屏液晶千兆网卡 / DVD / 光电鼠标 / DOS / 方正商务安全一键通 / 三年有限保修及上门

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HSUPA PCI Express Mini Card MF210开发文档Revision1.4November 6, 2009产品名称：MF210公司名称：中兴通讯股份有限公司目录1概述 (2)2.执行标准 (2)3.技术说明 (3)3.1工作频段 (3)3.2承载业务 (3)3.3硬件技术参数 (4)4. 接口定义 (4)4.1 PCI Express Mini Card Specification (5)4.2 PIN Definition (5)5射频测试座 (6)5.1 射频测试座规格 (6)5.2 射频连接线 (6)5.3 主天线和分集连接器位置 (7)5.4射频测试座S参数测试 (7)5.4.1 主天线射频座技术参数 (7)5.4.2 分集天线射频座技术参数 (8)6．射频主要性能指标 (9)6.1 UMTS模式射频技术指标 (9)6.1.1最大发射功率 (9)6.1.2接收灵敏度 (9)6.2 GPRS/GSM/EDGE模式射频技术指标 (10)6.2.1发射输出功率 (10)6.2.2接收灵敏度 (10)7.天线 (11)7.1无源指标（推荐） (11)7.2有源指标（推荐） (11)7.3笔记本布局建议 (11)7.4天线尺寸及放置 (12)7.5分集天线设计 (12)1概述MF210是一款支持UMTS850（900）/1900/2100、GSM/GPRS/EDGE 850/900/1800/1900多频段HSUPA的PCI Express Mini Card无线网卡，可以提供移动环境下的WCDMA、GSM/GPRS、EDGE（EGPRS）和HSUPA高速数据接入服务。

表3-1 MF210的工作频段上行下行UMTS850 824 MHz — 849 MHz 869 MHz — 894 MHzUMTS900 880 MHz — 915 MHz 925 MHz — 960 MHzUMTS1900 1850 MHz — 1910 MHz 1930 MHz — 1990 MHzUMTS2100 1920 MHz — 1980 MHz 2110 MHz — 2170 MHzGSM850 824 MHz — 849MHz 869 MHz — 894 MHzGSM900 890 MHz — 915MHz 935 MHz — 960MHzGSM1800 1710 MHz — 1785MHz 1805 MHz — 1880MHzGSM1900 1850 MHz — 1910MHz 1930 MHz — 1990MHz3.2承载业务WCDMA模式下分组域承载业务：最大下行传输速率为384 Kbit/s，最大上行传输速率为384 Kbit/s；WCDMA模式下电路域承载业务：64Kbit/s数据业务；HSDPA支持最大下行传输速率为7.2Mbit/s；HSUPA支持最大上行传输速率为5.76Mbit/s；支持EDGE CLASS12/GPRS CLASS12分组域承载业务。

3.3硬件技术参数硬件技术参数如表3-2所示。

表3-2 MF210硬件技术参数Item Specifications Remarks Interface type PCI Express Mini Card NOTE1 Protocol HSUPA/HSDPA/UMTS/EDGE/GPRS/GSMFrequency HSUPA/HSDPA/UMTS2100/1900/850(900)MHz; EDGE/GPRS/GSM1900/1800/900/850MHz HSDPA 7.2Mbps DLTransmissionHSUPA 5.76Mbps ULAverage： 1.20W NOTE2PowerMaximum：2.2W USIM&SIM Standard 6 PIN InterfaceAntenna Integrated with the notebookRx Diversity Support (2100/1900/850（900）MHz) NOTE3Equalization SupportStorage temperature -20℃ ~ +85℃Operation temperature -10℃ ~ +70℃System Required Windows 2K/XP, VistaDimensions About 51mm * 30mm * 4.7mm NOTE4Weight About30gCertification & Approval CE certification, ROHSChipset MSM6290+PM6658+RTR6285(RTR6280)NOTE5 NOTE1: The interface type does accord with 《PCI Express Mini Card Electromechanical Specification Revision 1.2, October 26 2007》.NOTE2: The average power dissipation of MF210 is tested when Tx power is 15dBm.NOTE3: Rx Diversity is selectable according to user customizationNOTE4: Type F2 is Full-Mini with bottom-side keep outs, and is compatible with type F1.NOTE5: RTR6285 is RF chip with Rx Diversity, RTR6280 is without Rx Diversity.4. 接口定义4.1 PCI Express Mini Card Specification见附件《PCI Express Mini Card Electromechanical Specification Revision 1.2，October 26 2007》。

4.2 PIN Definition表4-1 HSUPA PCI Express Mini Card MF210的管脚定义PIN# NAME ZTE's definition PIN#NAME ZTE's definition1 WAKE# Reserved2 3.3Vaux VDD_3V33 COEX1 Reserved4 GND GND5 COEX2 Reserved6 1.5V Reserved7 CLKREQ# Reserved 8 UIM_PWR USIM_POWER9 GND GND 10 UIM_DATA USIM_DATA11 REFCLK- Reserved 12 UIM_CLK USIM_CLK13 REFCLK+ Reserved 14 UIM_RESET USIM_RESET15 GND GND16 UIM_VPP USIM_VPP17 Reserved(UIM_C8) Reserved 18 GND GND19 Reserved(UIM_C4) Reserved 20 W_DISABLE# W_DISABLE_N21 GND GND22 PERST# PERST_N23 PERn0 Reserved 24 +3.3Vaux VDD_3V325 PERp0 Reserved 26 GND GND27 GND GND28 +1.5V Reserved29 GND GND30 SMB_CLK Reserved31 PETn0 Reserved 32 SMB_DATA Reserved33 PETp0 Reserved 34 GND GND35 GND GND36 USB_D- USB_DM37 GND GND38 USB_D+ USB_DP39 +3.3Vaux VDD_3V340 GND GNDVDD_3V3 41 +3.3Vaux 42 LED_WWAN# LED_WWAN_N GND 43 GND 44 LED_WLAN# Reserved 45 Reserved Reserved 46 LED_WPAN#Reserved 47 Reserved Reserved 48 +1.5V Reserved GND49ReservedReserved50GNDVDD_3V351 Reserved Reserved 52 +3.3Vaux NOTE1：请笔记本厂商保证模块所采用信号接口符合《PCI Express Mini Card Electromechanical Specification Revision 1.2, October 26 2007》；NOTE2：笔记本侧USIM 卡信号需要增加ESD 保护，并由ZTE 确认，确保正常工作； NOTE3：MF210与笔记本联调时，测试标准需要双方沟通确定。

5射频测试座5.1 射频测试座规格射频测试座即天线连接器, 选用HRS公司 U.FL-R-SMT(10)。

主天线和分集天线使用同一规格射频测试座。

图5.1 射频测试座（HRS 公司 U.FL-R-SMT(10)）5.2 射频连接线Cable 直径、长度可由实际情况进行定制，建议选用HRS 公司的U.FL_LP_088.图5.2 对应的测试Cable5.3 主天线和分集连接器位置图3.3 主副天线连接器位置5.4射频测试座S参数测试5.4.1 主天线射频座技术参数W21009612 Tx 10562 Rx 9750Tx 10700 Rx 9888 Tx 10838 Rx S11 主天线射频座(加射频头补偿到开路点=1.7cm) 1922.4MHz 2112.4MHz1950.0MHz2140.0MHz1977.6MHz2167.6MHzLOG MAGNITUDE （dB）-5.631 -7.609 -12.698-6.916 -8.046 -12.980SWR（驻波）U 3.192 2.423 1.613 2.666 2.191 1.60019.495 Ω 42.280Ω 31.497Ω 21.148Ω 56.758Ω 39.787ΩSWITH CHART（IMPEDANCE）阻抗Ω-23182 jΩ -41.398jΩ +5.432jΩ -17.352jΩ-42.422 jΩ -18.648 jΩW8504132Tx 4357 Rx 4182 Tx 4407 Rx 4233 Tx 4458 RxS11 主天线射频座(加射频头补偿到开路点=1.7cm)826.4MHz 871.4MHz 836.4MHz881.4MHz846.6MHz 891.6MHzLOG MAGNITUDE （dB）-9.140 -2.827 -6.213 -17.862-9.891 -6.378SWR（驻波）U 2.069 6.164 2.917 1.294 1.929 2.95427.327 Ω 15.791Ω 19.877Ω 64.668Ω 42.382Ω 18.627ΩSWITH CHART（IMPEDANCE）阻抗Ω-15.405 jΩ -47.814jΩ -18.318jΩ+1.837 jΩ -29.435jΩ -5.922 jΩ5.4.2 分集天线射频座技术参数W21009612 Tx 10562 Rx 9750Tx 10700 Rx 9888 Tx 10838 Rx S11 分集射频座(加射频头补偿到开路点=1.7cm) 1922.4MHz 2112.4MHz1950.0MHz2140.0MHz1977.6MHz2167.6MHzLOG MAGNITUDE（dB）-3.677 -2.723 -3.364 -2.633 -3.152 -2.633 SWR（驻波）U 4.797 6.410 5.229 6.723 5.579 6.63936.374 Ω 14.207Ω 29.293Ω 13.061Ω 24.248Ω 12.630ΩSWITH CHART（IMPEDANCE）阻抗Ω-5.623 jΩ -44.360jΩ -67.686jΩ-42.628 jΩ-63.641 jΩ 40.325 jΩW8504132Tx 4357 Rx 4182 Tx 4407 Rx 4233 Tx 4458 RxS11 分集天线射频座(加射频头补偿到开路点=1.7cm)826.4MHz 871.4MHz 836.4MHz881.4MHz846.6MHz 891.6MHzLOG MAGNITUDE （dB）-1.831 -2.180 -2.633 -18.199-2.633 -7.993SWR（驻波）U 9.485 8.001 8.550 1.280 6.638 2.3255.267 Ω6.951Ω 5.864Ω 60.174Ω 7.689Ω 22.016ΩSWITH CHART（IMPEDANCE）阻抗Ω-683.104jmΩ -16.583 jΩ +2.172jΩ`-8.504 +7.111jΩ +6.885jΩ6．射频主要性能指标6.1 UMTS模式射频技术指标6.1.1最大发射功率UMTS2100/1900/850（900）在正常测试环境下，最大输出功率满足表6-1要求。