《数字电子技术》PPT课件
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Figure 8–1 A 2-bit asynchronous binary counter. Open file F08-01 to verify operation.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–11 A 2-bit synchronous binary counter.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–9 Two configurations of the 74LS93 asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.)
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–10 74LS93 connected as a modulus-12 counter.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–8 The 74LS93 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)
Figure 8–2 Timing diagram for the counter of Figure 8–1. As in previous chapters, output waveforms are shown in green.
Thomas L. Floyd Digital Fundamentals, 9e
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–7 Asynchronously clocked modulus-12 counter with asynchronous recycling.
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–3 Three-bit asynchronous binary counter and its timing diagram for one cycle. Open file F08-03 to verify operation.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–6 An asynchronously clocked decade counter with asynchronous recycling.
Fra Baidu bibliotek
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–5 Four-bit asynchronous binary counter and its timing diagram. Open file F08-05 and verify the operation.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–11 A 2-bit synchronous binary counter.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–9 Two configurations of the 74LS93 asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.)
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–10 74LS93 connected as a modulus-12 counter.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–8 The 74LS93 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)
Figure 8–2 Timing diagram for the counter of Figure 8–1. As in previous chapters, output waveforms are shown in green.
Thomas L. Floyd Digital Fundamentals, 9e
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–7 Asynchronously clocked modulus-12 counter with asynchronous recycling.
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–3 Three-bit asynchronous binary counter and its timing diagram for one cycle. Open file F08-03 to verify operation.
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–6 An asynchronously clocked decade counter with asynchronous recycling.
Fra Baidu bibliotek
Thomas L. Floyd Digital Fundamentals, 9e
可编辑课件
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 8–5 Four-bit asynchronous binary counter and its timing diagram. Open file F08-05 and verify the operation.