含有异步清零和计数使能的16位二进制加减可控计数器
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1．含有异步清零和计数使能的16位二进制加减可控计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt16 IS
PORT(EN,RST,UPD,CLK : IN STD_LOGIC;
OUT1: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END cnt16;
ARCHITECTURE bhv OF cnt16 IS
SIGNAL QQ:STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN
PROCESS(EN,RST,UPD)
BEGIN
IF RST='1' THEN
QQ<=(OTHERS=>'0'); --有复位信号清零
ELSIF EN='1' THEN --EN位高电平开始计数IF CLK'EVENT AND CLK='1' THEN
IF UPD='1' THEN --当UDP为1加计数
QQ<=QQ+1;
ELSE --当UDP不为1减计数
IF QQ > "0" THEN --当减到0时
QQ<=QQ-1; --给QQ全1
ELSE
QQ<=(OTHERS=>'1');
END IF;
END IF;
END IF;
END IF;
END PROCESS;
OUT1<=QQ;
END bhv;
图1-1 16位二进制加减可控计数器的RTL图图1-2 16位二进制加减可控计数器的波形仿真图
2.1 计数器和译码器合起来的程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4_YM IS
PORT(CLK,RST,ENA:IN STD_LOGIC;
COUT:OUT STD_LOGIC;
LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END CNT4_YM;
ARCHITECTURE BEHV OF CNT4_YM IS
SIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
PROCESS(CLK,RST,ENA)
BEGIN
IF RST='1' THEN CQI<=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF ENA='1' THEN
IF CQI<9 THEN CQI<=CQI+1;
ELSE CQI<=(OTHERS=>'0');
END IF;
END IF;
END IF;
IF CQI=9 THEN COUT<='1';
ELSE COUT<='0';
END IF;
END PROCESS;
PROCESS(CQI)
BEGIN
CASE CQI IS
WHEN"0000"=>LED7S<="0111111";
WHEN"0001"=>LED7S<="0000110";
WHEN"0010"=>LED7S<="1011011";
WHEN"0011"=>LED7S<="1001111";
WHEN"0100"=>LED7S<="1100110";
WHEN"0101"=>LED7S<="1101101";
WHEN"0110"=>LED7S<="1111101";
WHEN"0111"=>LED7S<="0000111";
WHEN"1000"=>LED7S<="1111111";
WHEN"1001"=>LED7S<="1101111";
WHEN"1010"=>LED7S<="1110111";
WHEN"1011"=>LED7S<="1111100";
WHEN"1100"=>LED7S<="0111001";
WHEN"1101"=>LED7S<="1011110";
WHEN"1110"=>LED7S<="1111001";
WHEN"1111"=>LED7S<="1110001";
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
END BEHV; 2.2 计数器和译码器分开的程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JSYM IS
PORT(CLK,RST,ENA:IN STD_LOGIC;
COUT:OUT STD_LOGIC;
OUTY:OUTSTD_LOGIC_VECTOR(3 DOWNTO 0)); END JSYM;
ARCHITECTURE BEHV OF JSYM IS
BEGIN
PROCESS(CLK,RST,ENA)
V ARIABLE CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF RST='1' THEN CQI:=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF ENA='1' THEN
IF CQI<9 THEN CQI:=CQI+1;
ELSE CQI:=(OTHERS=>'0');
END IF;
END IF;
END IF;
IF CQI=9 THEN COUT<='1';
ELSE COUT<='0';
END IF;
OUTY<=CQI;
END PROCESS;
END BEHV;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DECL7S IS
PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END DECL7S;
ARCHITECTURE BEHV OF DECL7S IS
BEGIN
PROCESS(A)
BEGIN
CASE A IS
WHEN"0000"=>LED7S<="0111111";
WHEN"0001"=>LED7S<="0000110";
WHEN"0010"=>LED7S<="1011011";
WHEN"0011"=>LED7S<="1001111";
WHEN"0100"=>LED7S<="1100110";
WHEN"0100"=>LED7S<="1101101";
WHEN"0101"=>LED7S<="1111101";
WHEN"0110"=>LED7S<="0000111";
WHEN"0111"=>LED7S<="1111111";
WHEN"1000"=>LED7S<="1101111";
WHEN"1010"=>LED7S<="1110111";
WHEN"1011"=>LED7S<="1111100";
WHEN"1100"=>LED7S<="0111001";
WHEN"1101"=>LED7S<="1011110";
WHEN"1110"=>LED7S<="1111001";
WHEN"1111"=>LED7S<="1110001";
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
END;