集成电路设计自动化 讲义 Lect07_Current_Amplifier

s) p2
See derivation in the following pages
2015-9
Lecture 7
slide 16
Approximations
Y=G : gm2 + sCGS ;
Y=L : GL + sCL ;
D(s) = [1+ RSYG ][1+ rd 0YL ] + Aig RSYL [ ][ ] = 1+ RS (gm2 + sCGS ) 1+ rd 0 (GL + sCL ) + Aig RS (GL + sCL )
Load GL CL
gm0 (vG − vS )
rd 0
CGS 0
gm2
(Biblioteka Baidu)
M2 is diode connected
CGS 2
1 = vGS 2 gm2 iDS 2
RS Vin,d / 2
2015-9
Lecture 7
slide 11
Small-signal Analysis (cont’d)
Vod 2
+
1 rdo
Vod 2
− VS
+
gmo (VG
− VS
)
= 0
(1)
RS Vi,d / 2
@ Source:
−YL
Vod 2
+ YG (VG
− VS=)
1 RS
VS
−
Vid 2
(2)
( ) (1
+
rdoYL
)
Vod 2
+
1 + rdo gmo
(VG −VS ) −VG =0
−
RSYL
out1
I0
out2
M0 M2
M3 M1
Vin0
Vin1
Symmetric current amplifier
I0
M0
Vin0
I1
out M1
Vin1
Asymmetric current amplifier
2015-9
Lecture 7
slide 3
Symmetric: Detailed Analysis
slide 7
Math (cont’d)
∆= Vin K ( ID3 − ID2 )
∆I ≡ ID2 − ID3 =±I0
1−
1 −
∆V K I0
2 2
the left end
= I0 ID3 + ID2
(Limiting values)
2015-9
If I= D2 I0; I= D3 0 If = ID2 0; = ID3 I0
( ) ( ) D(s) =GL B + s CL B + RS rd 0GLCGS + s2 RS rd 0CGSCL
{ } = GLB + s (CLB + EGL ) + s2 ( ECL ) { } = GLB + s ( BCL + GLE ) + s2 ( ECL )
2015-9
= (GL + sCL )(B + sE) = 0
=±
I02
−
I0
−
∆V K
2 2
=± I 0
1−
1 −
∆V K I0
2 2
2 ID2ID3 = I0 − (∆V / K )2
2015-9
∆I ≡ ID2 − ID3 =±I0
1−
1 −
∆V K I0
2
2
Next we get the limiting values ...
Lecture 7
2015-9
Lecture 7
slide 10
Symmetric: Small-signal Analysis
vout,d / 2 (D)
vg
rd 0
(G)
CGS 0
(S) Vin,d / 2
CGS 2
Half circuit small-signal model
vout,d / 2 (D)
vG (G)
{ } ( ) ( ) (1+ RSYG )(1+ rdoYL ) + RSYL 1+ rdo gmo vod =1+ rdo gmo vid
AC gain
A(=s) v= od
1 + gm0rd 0
vid [(1+ YGrS )rd 0 + (1+ gm0rd 0 )RS ]YL + (1+ YG RS )
Lecture 7
slide 18
(cont’d)
D(s) = (GL + sCL )(B + sE) = 0
p1
=
GL CL
{ }( )( ) A(s) =
Aig
GL[rd 0 (1 + gm2RS ) + Aig RS ]
1+
s p1
1+
s p2
p=2
B= E
rd 0 (1 + gm2 RS ) + Aig RS (CGS 0 + CGS 2 )rd 0 RS
YG :=gm2 + s(CGS 0 + CGS 2 ) =gm2 + sCGS
D(s) ≡ (1+ RSYG )(1+ rd 0YL ) + Aig RSYL
CGS (CGS 0 + CGS 2 )
A(s) =
Aig
{ } GL[rd 0 (1+ gm2RS ) + Aig RS ]
(1 +
s )(1+ p1
{ ( )} (1+ RSYG )(1+ rdoYL ) + RSYL 1+ rdo gmo
Vo±d 2
+ (rdo gmo
− RSYG )VG
( ) =
1 + rdo gmo
Vid± 2
cancelling the commonmode term
2015-9
Lecture 7
slide 14
Symmetric: Small-signal analysis
Mixed-Signal Design and Automation Methods 混合信号电路设计与自动化方法
Lecture 7 Analysis of Current Amplifiers
Prof. Guoyong Shi
shiguoyong@sjtu.edu.cn
Department of Micro/Nano-electronics Shanghai Jiao Tong University Fall 2015
I. Symmetric current amplifier (DC, AC analysis)
2014-9-11
Lecture 7
slide 4
Symmetric Current Amplifier
out1
NI0 2
M0 M2
I0
V2 in0
out2
I out
NI0 2
M3 M1
I0 2
Vin1
Positive input ∆ voltage switches on the right transistor (M3) and proportionally the drain current of the right outer transistor (M1). Negative input ∆ voltage produces the opposite switching.
= 1+ RS (gm2 + sCGS ) + rd 0 (GL + sCL ) + RS rd 0 (gm2 + sCGS )(GL + sCL ) + Aig RS (GL + sCL )
Terms of s0:
Terms of s1: Terms of s2:
2015-9
= 1 + RS gm2 + rd 0GL + RS rd 0 gm2GL + Aig RSGL
ID2 )
(taking square)
( )
∆V K
2
=
2
ID3 − ID2 = ID3 + ID2 − 2 ID2ID3
(solve)
2 ID2 ID3=
Lecture 7
I0
−
∆V K
2
=I0 ID3 + ID2
slide 6
Math (cont’d) ID3 + ID2 = I0
( ) ( ) ∆I ≡ ID2 − ID3 = ± ID2 − ID3 2 = ± ID2 + ID3 2 − 4ID2ID3
∆Iout ≡ ID2 − ID3
∆Iout
∆Vin
∆Vin ≡ Vin0 − Vin1
HW: Please verify this circuit using HSPICE.
2015-9
Lecture 7
slide 5
DC Analysis (Math)
VGS=3 VG − V1;
VGS=2 VG − V0 ;
vout,d / 2 (D)
rd 0 GL CL
gm0 (vG − vS ) CGS 0
(S)
vG (G) gm2
CGS 2
1 = vGS 2 gm2 iDS 2
RS Vin,d / 2
vout,d / 2 (D)
Y=L : GL + sCL
YL
rd 0
YG :=gm2 + s(CGS 0 + CGS 2 )
Lecture 7
⇒ ∆Vin =−K I0 ∆I =+I0
⇒ ∆Vin =+K I0 ∆I =−I0 the right end
slide 8
DC Characteristics
∆Vin =−K I0 ∆Iout = +I0
∆Vin =+K I0 ∆Iout = −I0
∆Iout ≡ ID2 − ID3
= RSCGS + rd 0CL + RS rd 0 (gm2CL + GLCGS ) + Aig RSCL
= RS rd 0CGSCL
Lecture 7
slide 17
Approximation (cont’d)
Terms of s0: = GL rd 0 (1+ RS gm2 ) + Aig RS = GL B
Terms of s1: =CL rd 0 (1 + RS gm2 ) + Aig RS + RS rd 0GLCGS =CL B + RS rd 0GLCGS
Terms= of s2: R= S rd 0CGSCL ECL
B ≡ rd 0 (1+ RS gm2 ) + Aig RS
E ≡ RS rd 0CGS
The 2nd pole is far apart from the 1st one; practically can be considered as a one-pole system defined by the load (GL // CL).
2015-9
inverting amplifier
∆Vin =−K I0
2015-9
∆Vin :=V0 −V1
Lecture 7
∆Vin =+K I0
slide 9
Symmetric Current Amplifier - Summary
∆Iout ≡ ID2 − ID3
VG
V0
V1
∆Vin ≡ V0 −V1
Outline
• Symmetric current amplifier (DC, AC analysis) • Asymmetric current amplifier (DC, AC analysis)
2015-9
Lecture 7
slide 2
Useful Current Amplifier Cells
vG (G)
gm0 (vG − vS ) YG (S)
2015-9
Lecture 7
RS Vin,d / 2
slide 12
(cont’d)
out vo,d / 2 (D)
YL
rd 0
in
By (1) By (2)
2015-9
vG
gm0 (vG − vS ) YG
(S)
(G)
@ Drain:
YL
VG
∆Vin ≡ V0 − V1= VGS3 − VGS 2
V0 = ∆V K (
2015-9
= I D
µnCox (W 2
/
L) (VGS
− VTH )2
VGS − VTH = K ID
V1
K=
2
= ∆V
K(
ID3 −
ID2 )
µnCox (W / L)2
ID3 + ID2 = I0
I0
ID3 −
Vod 2
+ (1+ RSYG )(VG
−VS ) −VG
=− Vid 2
Lecture 7
slide 13
(cont’d)
( ) (1
+
rdoYL
)
Vod 2
+
1 + rdo gmo
(VG −VS ) −VG =0
+
−
RSYL
Vod 2
+ (1+ RSYG )(VG
−VS ) −VG
=− Vid 2
A(s) =
Aig
(1+ YG RS )(1+ rd 0YL ) + Aig RSYL
Aig = 1 + gm0rd 0
2015-9
Lecture 7
slide 15
AC (cont’d)
A(s)
Aig
≡ Aig
(1+ RSYG )(1+ rd 0YL ) + Aig RSYL D(s)
Y=L : GL + sCL ;
×(1+ RSYG )
×(−1)(1+ rdo gmo )
(1
+
RSYG
)(1
+
rdoYL
)
Vod 2
− (1+ RSYG )VG
( ) ( ) ( ) + RSYL
1 + rdo gmo
Vod 2
+
1 + rdo gmo
VG =
1 + rdo gmo
Vid 2
The other half circuit will give a similar equation for Vid - and Vod -.