Quartus II时序优化策略

Tclk1 Tco
Data Valid
Tdata
REG2.D Data Valid
Data Arrival Time = launch edge + Tclk1 + Tco +Tdata
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 20
适配器布局布线设置
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 9
物理综合优化
n
在布局布线阶段 Quartus II也可以 对设计网表进行 优化
− 改进某些布局的结
果 − 补偿适配器的布线 延时
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 10
综合网表优化
n n
在综合期间进一步优化网表 优化类型选择
− WYSIWYG 基元重新综合 − 门级寄存器重新定时
建立/修改编译报告中指出的节点
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 6
异步信号流水线工作
n
在非常快的时钟域，加入流水线寄存器，以减小 延时。
Added pipeline stage
D aclr aclr aclr Q
aclr
aclr
D
Q
D
Q aclr aclr
Global clock delay
D
Q
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 13
寄存器重新定时
n
比流水线使用更少的寄存器
− 权衡关键路径和非关键路径的延时 − 在逻辑单元（LE）级进行操作 − 不改变逻辑功能
D Q
10 ns
D Q
5 ns
D Q
D Q
7 ns
D Q
8 ns
D Q
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 15
时序问题分析
n
典型的同步时序模型
−
寄存器可以是FPGA内部的或外部的
REG1 Input Failure Output Failure Failure within Clock Domain
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 17
Clock Arrival Time = latch edge + Tclk2
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 21
Data Arrival Time
n
The time for data to arrive at destination register ’s D input
REG1
PRE
Tdata
Comb. Logic
REG2
PRE
D
Qห้องสมุดไป่ตู้
D
Q
Tclk1
CLR
CLR
TCO Launch Edge CLK REG1.CLK REG1.Q
时序优化议题2
n n n n n
一般建议 分析时序问题 解决典型时序问题 优化实例 优化总结
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 16
物理综合优化
n
优化类型选项
− 性能优化 l 组合逻辑 l 异步信号流水线工作 l 寄存器复制 l 寄存器重新定时 − 面积优化 l 组合逻辑 l 逻辑至寄存器映射
n
努力等级
− 综合考虑性能和编译时间 − 正常、额外和快速
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 11
Clock Arrival Time
n
The time for clock to arrive at destination register ’s clock input
REG1
PRE
REG2
D
Q
Comb. Logic
PRE
D
Q
CLR
CLR
Tclk2 Latch Edge CLK
Tclk2
REG2.CLK
组合逻辑
n
LE内部交换查找表 (LUT)， 以减少关键通路LE级 数
a b - critical c d e f g
LUT
LUT
a e c d b f g
LUT
LUT
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 12
DATA
D PRE Q
CLK
Tsu Th
DATA Valid
CLK
CLR
Setup:
The minimum time data signal must be stable BEFORE clock edge The minimum time data signal must be stable AFTER clock edge
一般建议
n n n
针对时钟 针对I/O 针对异步控制信号
n
大多数建议可以在Quartus II软件时序优化向导（ Timing Optimization Advisor） 和Quartus II Handbook找到
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 18
Setup & Hold
Quartus II 时序优化策略
© 2009 Altera Corporation 1
时序优化议题1
n n n n n
一般建议 分析时序问题 解决典型的时序问题 优化实例 优化总结
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2
寄存器复制
n
大扇出寄存器或者组合逻辑复制和布局，以减小 延时
N
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 14
时钟信号
n n n
逻辑综合速度优化 网表优化 物理综合
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 4
门级寄存器重新定时
n n n
在组合逻辑之间移动寄存器，以均衡时序 综合考虑关键和非关键路径 在门级进行改动
D Q >
10 ns
D Q >
5 ns
D Q >
D Q >
7 ns
D Q >
8 ns
D Q >
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 8
Together, the setup time and hold time form a Data Required Window, the time around a clock edge in which data must be stable.
Hold:
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 19
速度优化设置
n n
选择速度优化
− 默认是速度和面积均衡balanced选项
可能导致逻辑资源增加
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 5
REG2 Internal External Internal
External Internal Internal
Launch & Latch Edges
Launch Edge
CLK DATA Data Valid
Latch Edge
Launch Edge: Latch Edge:
the edge which “launches” the data from source register the edge which “latches” the data at destination register (with respect to the launch edge, selected by timing analyzer; typically 1 cycle)
WYSIWYG 基元重新综合
n
将第三方原子网表去映射回 逻辑门，然后重新映射到 Altera基元
−
使用集成综合时，不需要
n
需要考虑的
−
节点名称会变化 − 第三方综合属性可能会丢失 l 保留/保持 − 某些寄存器可能会被综合掉
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 7