Quartus+II时序优化策略
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©2009 Altera Corporation
©2009 Altera Corporation
©2009 Altera Corporation
©2009 Altera Corporation
©2009 Altera Corporation
©2009 Altera Corporation
©2009 Altera Corporation
©2009 Altera Corporation
©2009 Altera Corporation
Physical Synthesis
Types
− Targeting performance during synthesis and/or fitting Combinational logic Register retiming Asynchronous signal pipelining Register duplication Effort
− Trades performance vs. compile time − Specifies location (synthesis and/or fitting) of compilation time impact − Fast, Normal, or Extra
− Targeting fitting Physical synthesis for combinational logic Logic to memory mapping
New or modified nodes appear in Compilation Report
Tcl: set_global_assignment –name PHYSICAL_SYNTHESIS_EFFORT
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 11 11
Combinational Logic
Swaps look-up table (LUT) ports within LEs to reduce critical path LEs
a b - critical c d e f g
LUT
LUT
a e c d b f g
LUT
LUT
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 12 12
Gate-Level Register Retiming
Moves registers across combinatorial logic to balance timing Trades between critical & non-critical paths Makes changes at gate level Does not change logic functionality
D Q >
10 ns
D Q >
5 ns
D Q >
D Q >
7 ns
D Q >
8 ns
D Q >
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 13 13
Asynchronous Control Signals
Improve recovery & removal timing Make control signal non-global
− Project-wide Assignments ⇒ Settings ⇒ Fitter Settings ⇒ More Settings − Individually Set Global Signal logic option to Off
Enable Automatic asynchronous signal pipelining option (physical synthesis)
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 14 14
Asynchronous Signal Pipelining
Adds pipeline registers to asynchronous clear or load signals in very fast clock domains
Added pipeline stage
D aclr aclr aclr Q
aclr
aclr
D
Q
D
Q aclr aclr
Global clock delay
D
Q
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 15 15