EDA实验编程
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实验三、数字频率计
4位数字频率计控制模块
module
fre_pm1(clk,rst,count_en,count_clr,load); input clk,rst;output count_en,count_clr,load;reg
count_en,load;
always @(posedge clk)
begin if(rst) begin count_en<=0;load<=1;end
else begin count_en<=~count_en;
load<=~count_en;
end
end
assign count_clr=~clk&load; endmodule
四位频率计计数子模块module a1(out,cout,en,clr,clk);
input en,clr,clk;output[3:0] out;output cout;reg[3:0] out;
always @(posedge clk or posedge clr)
begin if(clr) out<=0;
else if(en) begin if(out==9) out<=0;else out<=out+1;end
end
assign cout=((out==9)&en)?1:0; endmodule
十六位锁存器模块
module b1(qo,din,load);
input load;input[15:0] din;output[15:0] qo;reg[15:0] qo;
always @(posedge load)
begin qo=din;end
endmodule
实验四英文之母显示电路
module abcd(clr,clk,a,b,c,d,e,f,g,w); input clr,clk;
output a,b,c,d,e,f,g,w;
reg[3:0] out;
reg a,b,c,d,e,f,g,w;
always @(posedge clk or posedge clr) begin if(clr) out<=0;
else
begin if(out==15) out<=0;
else out<=out+1;
end
end
always @(out)
begin
case(out)
4'h0:{a,b,c,d,e,f,g}=7'b1111110;
4'h1:{a,b,c,d,e,f,g}=7'b0110000;
4'h2:{a,b,c,d,e,f,g}=7'b1101101; 4'h3:{a,b,c,d,e,f,g}=7'b1111001;
4'h4:{a,b,c,d,e,f,g}=7'b0110011;
4'h5:{a,b,c,d,e,f,g}=7'b1011011;
4'h6:{a,b,c,d,e,f,g}=7'b1011111;
4'h7:{a,b,c,d,e,f,g}=7'b1110000;
4'h8:{a,b,c,d,e,f,g}=7'b1111111;
4'h9:{a,b,c,d,e,f,g}=7'b1110011;
4'ha:{a,b,c,d,e,f,g}=7'b1110111;
4'hb:{a,b,c,d,e,f,g}=7'b0011111;
4'hc:{a,b,c,d,e,f,g}=7'b1001110;
4'hd:{a,b,c,d,e,f,g}=7'b0111101;
4'he:{a,b,c,d,e,f,g}=7'b1001111;
4'hf:{a,b,c,d,e,f,g}=7'b1000111; default:{a,b,c,d,e,f,g}=7'b0000001; endcase
w=1;
end
endmodule
实验五序列检测器
module lychy(x,z,clk,reset,state);
input x,clk,reset;output z;output[3:0]state; reg[3:0]state;reg z;
parameter
s0='b000,s1='b001,s2='b010,s3='b011,s4='b10 0,s5='b101,s6='b110,s7='b111;
always @(posedge clk)
begin if(reset) begin state<=s0;z<=0;end else casex(state)
s0: begin
if(x==0) begin state<=s0;z<=0;end
else begin state<=s1;z<=0;end
end
s1: begin
if(x==0) begin state<=s0;z<=0;end
else begin state<=s2;z<=0;end
end
s2: begin
if(x==0) begin state<=s0;z<=0;end
else begin state<=s3;z<=0;end
end
s3: begin
if(x==0) begin state<=s4;z<=0;end
else begin state<=s3;z<=0;end
end
s4: begin
if(x==0) begin state<=s5;z<=0;end
else begin state<=s1;z<=0;end
end
s5: begin
if(x==0) begin state<=s0;z<=0;end
else begin state<=s6;z<=0;end
end
s6: begin
if(x==0) begin state<=s7;z<=1;end
else begin state<=s2;z<=0;end
end
s7: begin
if(x==0) begin state<=s0;z<=0;end
else begin state<=s1;z<=0;end
end
default: state<=s0;
endcase
end
endmodule
实验六、数字频率计的Verilog HDL语言实现实验一八三译码器和模13BCD
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