指令系统 教学课件.ppt

ARM指令的一般编码格式
31 28 27 26 25 24 21 20 19 16 15 12 11
0
cond 00 X opcode S Rn Rd Shifter-operand
opcode: 指令操作符编码 cond: 指令执行条件编码 S: 指令的操作是否影响CPSR的值 Rn: 包含第一个操作数的寄存器编码 Rd: 目标寄存器编码 Shifter_operand: 第二个操作数
Harvard can’t use self-modifying code. Harvard allows two simultaneous
memory fetches. Most DSPs use Harvard architecture for
streaming data:
greater memory bandwidth; more predictable bandwidth.
六个版本
ARMv1 ~ ARMv6
ARM体系结构的扩充
Thumb (T variant): 16位指令集，用以改善 指令密度；
DSP (E variant): 用于DSP应用的算术运算指 令集；
Jazeller (J variant): 允许直接执行Java字节
码
什么是指令密度？
Load-store Architecture
指令集仅能处理(如ADD、SUB等)寄存器中(或 指令中直接指定)的值，而且总是将处理结果 放回寄存器中。针对存储器的唯一操作是将存 储器的值装入寄存器(load指令)，或将寄存器 的值存到存储器(store指令)。
相比较，典型的CISC处理器允许将存储器中的 值加(ADD)到寄存器，有时还允许将寄存器的 值加(ADD)到存储器中。
Some registers are not visible (e.g. IR).
Multiple implementations
Successful architectures have several implementations:
varying clock speeds; different bus widths; different cache sizes; etc.
bytes. ARM addresses can be 32 bits long. Address refers to byte.
Address 4 starts at byte 4.
Can be configured at power-up as either little- or big-endian mode.
1. Computer Architecture Taxonomy
What is architecture?
Architecture & Organization 1
Architecture is those attributes visible to the programmer
Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques.
Instruction Set & Assembly Language Programming
Jianjian SONG Software Institute, Nanjing University
Content
Computer Architecture Taxonomy ARM Architecture Introduction ARM Instruction Set ARM Assembly Language Programming
Instruction set characteristics
Fixed vs. variable length. Addressing modes. Number of operands. Types of operands.
Programming model
Programming model: registers visible to the programmer.
ARM status bits
Every arithmetic, logical, or shifting operation sets CPSR bits:
N (negative), Z (zero), C (carry), V (overflow).
Examples:
-1 + 1 = 0: NZCV = 0110. 231-1+1 = -231: NZCV = 0101.
RISC vs. CISC
Complex instruction set computer (CISC):
many addressing modes; many operations.
Reduced instruction set computer (RISC):
load/store; pipelinable instructions.
Pseudo-ops
Some assembler directives don’t correspond directly to instructions:
Define current address. Reserve storage. Constants.
ARM programming model
Instructions Overview
Data instructions Move Instructions Load/Store instructions Comparison instructions Branch instructions
ARM data instructions
ARM具有RISC体系的一般特点：
大量寄存器 绝大多数操作都在寄存器中进行，通过Load/Store
的在内存和寄存器间传递数据。 寻址方式简单 采用固定长度的指令格式
此外，
小体积、低功耗、低成本、高性能 16位/32位双指令集 全球众多合作伙伴
ARM体系结构的版本和扩充
Why assembly language? One-to-one with instructions (more or less). Basic features:
One instruction per line. Labels provide names for addresses (usually in
by repeated addition?
Architecture & Organization 2
All Intel x86 family share the same basic architecture
The IBM System/370 family share the same basic architecture
first column). Instructions often start in later columns. Columns run to end of line.
ARM assembly language example
label1
ADR r4,c LDR r0,[r4] ; a comment ADR r4,d LDR r1,[r4] SUB r0,r0,r1 ; comment
执行同等操作序列的前提下，单位内存空间所容纳的机器指令数。
ARM体系结构版本的命名格式
命名字符串:
ARM vx (x: 指令集版本号，1~6) 表示变种的字符 (如 T, E, J ) 用字符x表示排除某种写功能。
ARM处理器系列
ARM7系列 ARM9系列 ARM9E系列 ARM10系列 SecureCore系列 Intel StrongARM Intel XScale
2. ARM Architecture Introduction
ARM (Advanced RISC Machines) ARM公司是一家设计公司，是IP 供应商，
靠转让设计许可证由合作伙伴生产各具 特色的芯片。
What is IP？Intellectual Property
ARM的特点
Basic format:
ADD r0,r1,r2 Computes r1+r2, stores in r0.
This gives code compatibility
At least backwards
Organization differs between different versions
von Neumann architecture
Memory holds data, instructions. Central processing unit (CPU) fetches
bit 31
byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3
little-endian
big-endian
ARM data types
Word is 32 bits long. Word can be divided into four 8-bit
instructions from memory.
Separate CPU and memory distinguishes programmable computer.
CPU registers help out: program counter (PC), instruction register (IR), general-purpose registers, etc.
ARM指令的基本寻址方式
寄存器寻址
例：ADD R0 , R1 , R2
立即数寻址
例：ADD R3 , R3 , #2
寄存器间接寻址
例：LDR R0 , [R3]
寄存器变址
例：LD百度文库 R0 , [R1, #4]
相对寻址
例：B rel
; (R1)+(R2)→R0 ; (R3)+2→R3 ; ((R3))→R0 ; ((R1)+4)→R0 ; (PC)+rel→PC
e.g. Is there a multiply instruction?
Organization is how features are implemented
Control signals, interfaces, memory technology. e.g. Is there a hardware multiply unit or is it done
CPU + memory
address
memory
data
2P0C0
CPU
200 ADD r5,r1,r3
ADDIrR5,r1,r3
Harvard architecture
address
data memory
data
PC
address
CPU
program memory data
von Neumann vs. Harvard
3. ARM Instruction Set
ARM assembly language ARM programming model ARM memory organization ARM data operations ARM flow of control
Assembly language
r0
r8
r1
r9
31
0
r2
r10
r3
r11
CPSR
r4
r12
r5
r13
r6
r14
NZCV
r7
r15 (PC)
Endianness
Relationship between bit and byte/word ordering defines endianness:
bit 31
bit 0 bit 0