半导体封装制程与设备材料知识介绍教学文案

Quad Flat Package (QFP） Microprocessor
BALL Grid Array (BGA） Microprocessor
封 裝 型 式 (PACKAGE)
Through Hole Mount
DIP
Dual In-line Package
Shape
Typical Features
Material Lead Pitch No of I/O
Ceramic Plastic
2.54 mm (100miles)
8 ~64
SIP
Single In-line Package
Plastic
2.54 mm (100miles) 1 direction
lead
3~25
Through Hole Mount
IC制造开始
Wafer Cutting (晶圆切断)
Wafer Reduce (晶圆减薄)
Oxidization (氧化处理)
Lithography (微影)
Etching (蚀刻)
后段封装开始
Diffusion Ion
Implantation (扩散离子植入)
Grind & Dicing (晶圓研磨及切割)
ZIP
Zigzag In-line Package
S-DIP
Shrink Dual In-line
Package
封裝型式
Shape
Typical Features
Material Lead Pitch No of I/O
Plastic
2.54 mm (100miles) 1 direction
lead
Die Attach (上片)
Deposition (沉积)
WireBonding (焊线)
Wafer Inspection (晶圆检查) 前段結束
Molding (塑封)
Laser mark (激光印字)
Laser Cut & package saw Testing
(切割成型)
(测试)
Package (包装)
製造完成
封装型式概述
IC封装型式可以分为两大类，一为引脚插入型，另一为表面黏着型
构装型态
构装名称
常见应用产品
Single In-Line Package (SIP）
Dual In-Line Package (DIP）
Zigzag In-Line Package (ZIP） Small Outline Package (SOP）
Ceramic Plastic
2.54 mm (100miles) half-size pitch in the
width direction
24~32
Ceramic Plastic
2.54 mm (100miles)
Surface Mount
SOP Small Outline Package
QFP Quad-Flat
Material Lead Pitch No of I/O
Ceramic
1.27 mm (50miles) j-shape bend 4 direction
lead
18~124
Ceramic
0.5 mm
32~200
SanDisk Assembly Main Process
SMT
(Optional)
Laser Cut
Package Saw
Cleaner
Memory Test
Card Asy
Card Test
Plastic Leaded Chip Carrier (PLCC）
Small Outline Package (SOJ）
Power Transistor
SRAM, ROM, EPROM, EEPROM, FLASH, Micro controller
DRAM, SRAM
Linear, Logic, DRAM, SRAM 256K DRAM, ROM, SRAM, EPROM, EEPROM, FLASH, Micro controller DRAM, SRAM, EPROM, EEPROM, FLASH
Pack
封裝型式
Shape
Typical Features
Material Lead Pitch No of I/O
Plastic
1.27 mm (50miles) 2 direction
lead
8 ~40
Plastic
1.0, 0.8, 0.65 mm 4 direction
lead
88~200
Surface Mount
16~24
Plastic
1.778 mm (70miles)
20 ~64
Through Hole Mount
SK-DIP
Skinny Dual In-line
Package
PBGA
Pin Grid Array
封裝型式
Shape
Typical Features
Material Lead Pitch No of I/O
FPG
Flat Package of Glass
LCC
Leadless Chip
Carrier
封裝型式
Shape
Typical Features
Material Lead Pitch No of I/O
1.27, 0.762 mm (50, 30miles)
Ceramic 2, 4 direction lead
半导体封装制程与设备材料知识介绍
半导体封装制程概述
半导体前段晶圆wafer制程 半导体后段封装测试
封装前段（B/G-MOLD）－封装后段（MARK-PLANT）－测试
封装就是將前製程加工完成後所提供晶圓中之每 一顆IC晶粒獨立分離，並外接信號線至導線架上 分离而予以包覆包装测试直至IC成品。
半导体制程
20~80
Ceramic
1.27,1.016, 0.762 mm (50, 40, 30
miles)
20~40
Surface Mount
Leabharlann BaiduPLCC
Plastic Leaded Chip Carrier
VSQF
Very Small Quad Flatpack
封裝型式
Shape
Typical Features
Taping (Optional)
Grinding (Optional)
Detaping (Optional)
Wafer Mount
UV Cure (Optional)
Die Saw
Die Bond
Die Cure (Optional)
Plasma
Wire Bond
Molding
Post Mold Cure Laser mark