余三码计数器
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--底层设计实体计数器163
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity v74hc163 is
port( clk,clr_l,ld_l,ctp,ctt : in std_logic;
d: in unsigned (3 downto 0); --置数输入
q : out unsigned (3 downto 0); --计数输出
rco : buffer std_logic); --进位输出end v74hc163 ;
architecture behave of v74hc163 is
signal iq : unsigned (3 downto 0);
begin
process(clk, ctt, iq)
begin
if clk'event and clk='1' then
if clr_l = '0' then
iq <= (others =>'0'); --同步清0
elsif ld_l ='0' then iq<=d; --同步置数
elsif rco ='1' then iq <= d; --计数满重新计数
elsif (ctt and ctp) ='1' then iq<= iq+1 ; --计数end if;
end if;
if (iq=15) and (ctt='1') then rco<='1'; --计到15进位else rco<='0';
end if;
q<=iq;
end process;
end behave ;
--底层设计实体与非门
library ieee;
use ieee.std_logic_1164.all;
entity nand_gate is
port
( a,b:in std_logic;
nand_result:out std_logic);
end nand_gate;
architecture behave of nand_gate is
begin
nand_result<=not(a and b);
end behave;
--底层设计实体非门
library ieee;
use ieee.std_logic_1164.all;
entity not_gate is
port( c:in std_logic;
not_result:out std_logic);
end not_gate;
architecture behave of not_gate is
begin
not_result<=not c;
end behave;
--底层设计实体与门
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port( m,n: in std_logic;
and_result: out std_logic);
end and_gate;
architecture behave of and_gate is
begin
and_result<= m and n;
end behave;
--顶层设计实体
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity excess_3_code is --顶层实体
port( cp,ctto,ctpo,clr_lo,lb:in std_logic;
qo:buffer std_logic_vector(3 downto 0);
co:out std_logic);
end excess_3_code;
architecture behave of excess_3_code is
component v74hc163 is --component v74hc163 port(
clk,clr_l,ld_l,ctp,ctt:in std_logic;
d: in unsigned(3 downto 0);
q: buffer unsigned(3 downto 0);
rco: out std_logic);
end component;
component nand_gate is --component 与非port( a,b:in std_logic;
nand_result:out std_logic);
end component;
component not_gate is --component 非port( c:in std_logic;
not_result:out std_logic);
end component;
component and_gate is --component 与port( m,n:in std_logic;
and_result: out std_logic);
end component;
signal c1,c2:std_logic;
begin
G1:v74hc163 port map
(clk=>cp,clr_l=>clr_lo,ctp=>ctpo,ctt=>ctto,
ld_l=>c2,
d(0)=>'1',
d(1)=>'1',
d(2)=>'0',
d(3)=>'0',
q(0)=>qo(0),
q(1)=>qo(1),
q(2)=>qo(2),
q(3)=>qo(3));
G2:nand_gate port map
( a=>qo(2),b=>qo(3),nand_result=>c1);
G3:not_gate port map
( c=>c1, not_result=>co);
G4: and_gate port map
(m=>c1,n=>lb,and_result=>c2);
end behave;