VHDL二进制比较器代码(测试成功)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COMPARE IS

GENERIC(SIZE:INTEGER:=2);

PORT (DAT1,DAT2:IN STD_LOGIC_VECTOR(SIZE DOWNTO 1);

L,E,S:OUT STD_LOGIC);

END ENTITY COMPARE;

ARCHITECTURE ART OF COMPARE IS

BEGIN

PROCESS(DAT1,DAT2)

BEGIN

IF(DAT1(SIZE-1 DOWNTO 1)>DAT2(SIZE-1 DOWNTO 1)) THEN

L<='1';E<='0';S<='0';

ELSIF (DAT1(SIZE-1 DOWNTO 1)

L<='0';E<='0';S<='1';

ElSIF (DAT1(SIZE-1 DOWNTO 1)=DAT2(SIZE-1 DOWNTO 1)) THEN

L<='0';E<='1';S<='0';

END IF;

END PROCESS;

END ARCHITECTURE ART;