EDA 常见实例源程序代码vhdl
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第4章用VHDL程序实现常用逻辑电路
4.1 组合逻辑电路设计
4.1.1 基本逻辑门
library ieee;
use iee.std_logic_1164.all;
entity jbm is
port(a,b: in bit;
f1,f2,f3,f4,f5,f: out bit);
end jbm;
architecture a of jbm is
begin
f1<=a and b; --构成与门
f2<=a or b; --构成或门
f<=not a; --构成非门
f3<=a nand b; --构成与非门
f4<=a nor b; --构成异或门
f5<=not(a xor b); --构成异或非门即同门
end;
4.1.2 三态门
library ieee;
use ieee.std_logic_1164.all;
entity tri_s is
port(enable: in std_logic;
datain: in std_logic_vector(7 downto 0);
dataout: out std_logic_vector(7 downto0));
end tri_s;
architecture bhv of tri_s is
begin
process(enable,datain)
begin
if enable='1' then
dataout<=datain;
else
dataout<="ZZZZZZZZ";
end if;
end process;
end bhv;
4.1.3 3-8译码器
library ieee;
use ieee.std_logic_1164.all;
entity decoder3_8 is
port(a,b,c,g1,g2a,g2b: in std_logic;
y: out std_logic_vector(7 downto 0));
end decoder3_8;
architecture a of decoder3_8 is
signal dz:std_logic_vector(2 downto 0);
begin
dz<=c&b&a;
process (dz,g1,g2a,g2b)
begin
if(g1='1'and g2a='0'and g2b='0')then
case dz is
when "000"=> y<="11111110";
when "001"=> y<="11111101";
when "010"=> y<="11111011";
when "011"=> y<="11110111";
when "100"=> y<="11101111";
when "101"=> y<="11011111";
when "110"=> y<="10111111";
when "111"=> y<="01111111";
when others=>y<="XXXXXXXX";
end case;
else
y<="11111111";
end if;
end process;
4.1.4 优先编码器
library ieee;
use ieee.std_logic_1164.all
entity coder is
port(din: in std_logic_vector(0 to 7);
output: out std_logic_vector(0 to 2));
end coder;
architecture behave of coder is
signal sint: std_logic_vevtor(4 downto 0);
begin
process(din)
begin
if (din(7)='0') then
output <= "000" ;
elsif (din(6)='0') then
output <= "100" ;
elsif (din(5)='0') then
output <= "010" ;
elsif (din(4)='0') then
output <= "110" ;
elsif (din(3)='0') then
output <= "001" ;
elsif (din(2)='0') then
output <= "101" ;
elsif (din(1)='0') then
output <= "011" ;
else
output <= "111" ;
end if;
end process;
end behav;
4.1.5 7段码译码器
library ieee;
use ieee.std_logic_1164.all
entity decl7s is
port (a: in std_logic_vector (3 downto 0);
led7s: out std_logic_vector(6 downto 0));
end decl7s;
architecture behave of decl7s is
begin
process(a)
begin
case a is
when "0000" => led7s <= "0111111" ;
when "0001" => led7s <= "0000110" ;
when "0010" => led7s <= "1011011" ;
when "0011" => led7s <= "1001111" ;
when "0100" => led7s <= "1100110" ;
when "0101" => led7s <= "1101101" ;
when "0110" => led7s <= "1111101" ;
when "0111" => led7s <= "0000111" ;
when "1000" => led7s <= "1111111" ;
when "1001" => led7s <= "1101111" ;
when "1010" => led7s <= "1110111" ;
when "1011" => led7s <= "1111100" ;
when "1100" => led7s <= "0111001" ;
when "1101" => led7s <= "1011110" ;
when "1110" => led7s <= "1111001" ;
when "1111" => led7s <= "1110001" ;
when others => null;
end case;
end process;
end behave;
4.1.6二-十进制BCD译码器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity bcdymq is
port(din : in integer range 15 downto 0;
a,b : out integer range 9 downto 0);
end;
architecture fpq1 of bcdymq is
begin
p1: process(din)
begin
if din<10 then
a< =din;
b< =0;
else
a< =din-10;