陶瓷电容静电防护特性

MLCC ESD characterization

Ron Demcko and Brian Ward

AVX

3900 Electronics Dive

Raleigh, NC 27604

919-878-6224/919-878-6470

ABSTRACT

Electronic systems are increasingly portable and miniature as a result of advanced integrated circuits; miniaturized power sources and high density I/Os.

Of these three driving forces, the IC trend of increased complexity and lower prices through manufacturing improvements and a physical size reduction trend called scaling impacts designers the most.

Scaling is a 3 dimensional shrinking of the IC structure, which allows more ICs to be built on a wafer – thus improving material utilization and manufacturing efficiency.

Scaling drives IC prices – which are so attractive that their use is cost effective virtually in any system and any place.

The flip side to scaling is that it creates ICs that are more susceptible to transient voltages due to thinner oxides and smaller metallization traces. Scaled ICs are highly susceptible to transient voltages. These transients may totally destroy the IC; damage the IC enough to cause infant mortality or cause incorrect data from operands.

The ideal method of transient voltage suppression is to clamp the transient voltage with a transient voltage suppressor (TVS). Multilayer Varistors (MLVs) are an ideal choice of TVS’s since they clamp voltage in their on state diverting the surge away from the sensitive electronics, and act as an EMI filter in their off state.

However, not all electronics can accept the extra cost of MLVs. In particular, past design practices on slower speed auto engine controllers (ECUs) with PCB layout optimized for input/output ports has exclusively used MLCCs to integrate transient voltages. Other examples exist such as gaming consoles. These relatively new miniature and highly portable systems are being exposed to wide varieties of harsh transient voltage environments.

This paper will concentrate on characterizing the ESD performance of a variety of multilayer ceramic capacitors in different case sizes and dielectrics. Test methods will employ an extreme series of ESD events.

Though testing is limited, a generic industry performance level will be shown for various size MLCCs.

PCB layout optimization recommendations will be given along with guidance as to the best MLCC available for design performance.

ESD Basics

Electrostatic Discharge is a sub nanosecond rise time event that is generated by charge transfer of materials in the tribo-electric material series.

ESD can be either positive or negative in polarity, contact or air discharge and repetitive or random in nature. An ESD event is typically modeled by a capacitor charged to a particular voltage level in series with a current limiting resistor. These models are in turn discharged at particular repetition rates to simulate a certain number of real world transients incident upon the DUT.

Several models exist which can be used to simulate specific transient sources that may inject ESD into a victim. Among the three most common models are: Charged Device Model, Machine Model and Human Body Model (HBM).

This paper concentrates on transient generation from the HBM with a capacitance of 150 pf and a resistance of 330 ohms.

HBM transients were injected via a Schaffner NSG 438 ESD gun using a 10 Hz rep rate and alternate polarity injection of the ESD event. For these tests, capacitors were first mounted on an FR4 material PCB. The parts were then read for production parameters of Capacitance, Dissipation Factor (DF) and Insulation Resistance (IR). A series of 10 positive pulses followed by 10 negative ESD pulses at a 10 Hz rep rate were injected into the capacitor by contact discharge. The capacitors were then tested for capacitance, DF and IR. Failures were determined by the tested capacitors inability to meet capacitance, DF or IR requirements. The failure definition is quite inexact and holds the possibility of error. That is, no long-term environmental tests were performed to confirm that passing parts are good. Likewise, not all circuits will experience failure when capacitance, Dissipation Factor and Insulation Resistance change outside specified limits.

It is critical to note that this test was aimed to parallel worst case brute testing seen at several sites. That is, an increasing number of customers do pass/fail system testing on end systems with 10 positive ESD pulses followed by 10 negative ESD pulses. These customers would like to get a rough idea of capacitor capability prior to completing a design.

Though there are many drawbacks to this method – it’s still being employed. The first disadvantage is that the industry does not need additional test methods. Perhaps the prime disadvantage to this method is that as the capacitor under test is struck with multiple pulses without being discharged so the charge and voltages accumulate on the capacitor with each strike. Even though recommendations are made to use more exacting standard tests some end users simply refuse to accept them.

Discussions with these customers eventually boil down to the likelihood of a system receiving repetitive strikes so quickly and the attenuation and integration effects that the system housing and PCBs transmission line characteristics present. The PCB transmission