信号灯控制状态机的verilog代码实例

主路口和支路口的信号灯控制状态机的verilog代码实例；
将testbench与源文件放在一个文件中，方便仿真；
//以下为正式代码，请做适当修改后采用modelsim仿真；
/////////////////////////////////////////////////
`define TRUE 1'b1
`define FALSE 1'b0
`define Y2RDELAY 3
`define R2GDELAY 2
module test_FSM_sig_control();
wire [1:0] main_sig, cntry_sig;
reg car_on_cntry_rd;
reg clock1,clear;
FSM_sig_control FSM_sig_control_v0(main_sig,cntry_sig, car_on_cntry_rd, clock1, clear);
initial
$monitor ($time, "main sig = %b, country sig = %b, car on cntry = %b", main_sig, cntry_sig, car_on_cntry_rd);
initial
begin
clock1 = `FALSE;
forever #5 clock1 = ~clock1;
end
initial
begin
clear = `TRUE;
repeat (5) @(negedge clock1);
clear = `FALSE;
end
initial
begin
car_on_cntry_rd = `FALSE;

repeat (20) @(negedge clock1);car_on_cntry_rd = `TRUE;
repeat (10) @(negedge clock1);car_on_cntry_rd = `FALSE;

repeat (20) @(negedge clock1);car_on_cntry_rd = `TRUE;
repeat (10) @(negedge clock1);car_on_cntry_rd = `FALSE;

repeat (20) @(negedge clock1);car_on_cntry_rd = `TRUE;
repeat (10) @(negedge clock1);car_on_cntry_rd = `FALSE;

repeat (10) @(negedge clock1);
$stop;

end

endmodule
module FSM_sig_control(hwy,cntry, X, clock1,clear);
output [1:0] hwy,cntry;
reg [1:0] hwy,cntry;
input X;
input clock1,clear;
parameter RED = 2'd0;
parameter YELLOW = 2'd1;
parameter GREEN = 2'd2;
parameter S0= 3'd0;
parameter S1= 3'd1;
parameter S2= 3'd2;
parameter S3= 3'd3;
parameter S4= 3'd4;
reg [2:0] state;
reg [2:0] next_state;
always @(posedge clock1)
if(clear)
state<=S0;
else
state <=next_state;

always @(state)
begin
hwy =GREEN;
cntry= RED;

case(state)
S0:;
S1: hwy =YELLOW;
S2: hwy=RED;
S3: begin
hwy =RED;
cntry = GREEN;
end
S4: begin
hwy =RED;
cntry = YELLOW;
end
endcase
end

always @(state or X)
begin
case(state)
S0: if(X)
next_state =S1;
else
next_state=S0;
S1: begin
repeat (`Y2RDELAY) @(posedge clock1)
next_state =S2;
end
S2: begin
repeat (`R2GDELAY) @(posedge clock1)
next_state =S3;
end
S3: if(X)
next_state =S3;
else
next_state=S4;
S4: begin
repeat (`Y2RDELAY) @(posedge clock1)
next_state =S0;
end
default: next_state = S0;
endcase
end

endmodule