TI(双四输入或非门)

2
DC Electrical Characteristics CD4002C
Symbol IDD PD VOL VOH VNL VNH IDN Parameter Quiescent Device Current Conditions VDD e 5 0V VDD e 10V
CD4012C Limits
b 0 35 b0 3 b 0 145 b 0 35
75 300 0 05 0 05 4 95 9 95 14 29 15 30 0 24 0 48 0 095 02
b 0 24 b0 2 b 0 095 b 0 24
4 95 9 95 15 30 15 30 03 06 0 12 0 25
b0 3 b 0 25 b 0 12 b0 3
Min
Max
Quiescent Device VDD e 5 0V Dissipation Package VDD e 10V Output Voltage Low Level Output Voltage High Level Noise Immunity (All Inputs) Noise Immunity (All Inputs) Output Drive Current N-Channel (4002) (Note 2) Output Drive Current N-Channel (4012) (Note 2) Output Drive Current P-Channel (4002) (Note 2) Output Drive Current P-Channel (4012) (Note 2) Input Current VDD e 5 0V VI e VDD IO e 0A VDD e 10V VI e VDD IO e 0A VDD e 5 0V VI e VSS IO e 0A VDD e 10V VI e VSS IO e 0A VDD e 5 0V VO t 3 6V IO e 0A VDD e 10V VO t 7 2V IO e 0A VDD e 5 0V VO s 0 95V IO e 0A VDD e 10V VO s 2 9V IO e 0A VDD e 5 0V VO e 0 4V VI e VDD VDD e 10V VO e 0 5V VI e VDD VDD e 5 0V VO e 0 4V VI e VDD VDD e 10V VO e 0 5V VI e VDD VDD e 5 0V VO e 2 5V VI e VSS VDD e 10V VO e 9 5V VI e VSS VDD e 5 0V VO e 2 5V VI e VSS VDD e 10V VO e 9 5V VI e VSS 4 95 9 95 15 30 14 29 0 35 0 72 0 145 03
b 55 C a 25 C
b 65 C to a 150 C
700 mW 500 mW VSS a 3 0V to VSS a 15V 260 C
DC Electrical Characteristics CD4002M
Symbol IDD PD VOL VOH VNL VNH IDN Parameter Quiescent Device Current Conditions VDD e 5 0V VDD e 10V
b0 5 b0 5
Quiescent Device VDD e 5 0V Dissipation Package VDD e 10V Output Voltage Low Level Output Voltage High Level Noise Immunity (All Inputs) Noise Immunity (All Inputs) Output Drive Current N-Channel (4002) (Note 2) Output Drive Current P-Channel (4002) (Note 2) Output Drive Current N-Channel (4012) (Note 2) Output Drive Current P-Channel (4012) (Note 2) Input Current VDD e 5 0V VI e VDD IO e 0A VDD e 10V VI e VDD IO e 0A VDD e 5 0V VI e VSS IO e 0A VDD e 10V VI e VSS IO e 0A VDD e 5 0V VO e 3 6V IO e 0A VDD e 10V VO e 7 2V IO e 0A VDD e 5 0V VO e 0 95V IO e 0A VDD e 10V VO e 2 9V IO e 0A VDD e 5 0V VO e 0 4V VI e VDD VDD e 10V VO e 0 5V VI e VDD VDD e 5 0V VO e 2 5V VI e VSS VDD e 10V VO e 9 5V VI e VSS VDD e 5 0V VO e 0 4V VI e VDD VDD e 10V VO e 0 5V VI e VDD VDD e 5 0V VO e 2 5V VI e VSS VDD e 10V VO e 9 5V VI e VSS 4 95 9 95 15 30 14 29 05 11
查询CD4002供应商
CD4002M CD4002C Dual 4-Input NOR Gate CD4012M CD4012C Dual 4-Input NAND Gate
March 1988
CD4002M CD4002C Dual 4-Input NOR Gate CD4012M CD4012C Dual 4-Input NAND Gate
Features
Y Y Y
Wide supply voltage range Low power High noise immunity
3 0V to 15V 10 nW (typ ) 0 45 VDD (typ )
Applications
Y Y Y Y
Automotive Data terminals Instrumentation Medical Electronics
b 55 C a 25 C a 85 C
Units 15 30 mA mA mW mW V V V V V V V V mA mA mA mA mA mA mA mA pA
Βιβλιοθήκη BaiduMin
Max 05 50 25 50 0 05 0 05
Min
Typ 0 005 0 005 0 025 0 05 0 0
Max 05 50 25 50 0 05 0 05
b0 5 b1 2
0 175 0 35
b 0 175 b0 4
IDP
II
10
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 IDN and IDP are tested one output at a time
Y Y Y Y
Alarm system Industrial controls Remote metering Computers
Connection Diagrams
CD4002 Dual-In-Line Package CD4012 Dual-In-Line Package
TL F 5940 – 1
General Description
These NOR and NAND gates are monolithic complementary MOS (CMOS) integrated circuits The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage This results in high noise immunity over a wide supply voltage range No DC power other than that caused by leakage current is consumed during static conditions All inputs are protected against static discharge and latching conditions
TL F 5940 – 2
Top View Order Number CD4002 or CD4012
Top View
C1995 National Semiconductor Corporation
TL F 5940
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications
a 125 C
Units mA mA mW mW V V V V V V V V mA mA mA mA mA mA mA mA pA
Min
Max 0 05 01 0 25 10 0 05 0 05
Min
Typ
Max
Min
Max 30 6 15 60 0 05 0 05
0 001 0 05 0 001 0 1 0 005 0 25 0 01 10 0 0 4 95 9 95 15 30 15 30 0 40 09
b 0 62 b 0 62
0 05 0 05 4 95 9 95 14 29 15 30 0 28 0 65
b 0 35 b 0 35
50 10 2 25 45 2 25 45 10 25
b2 0 b1 0
IDP
IDN
0 31 0 63
b 0 31 b 0 75
0 25 05
b 0 25 b0 6
05 06
Voltage at Any Pin Operating Temperature Range CD4002M CD4012M CD4002C CD4012C VSS b0 3V to VDD a 0 3V
b 55 C to a 125 C b 40 C to a 85 C
Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Operating Range (VDD) Lead Temperature (TL) (Soldering 10 seconds) CD4012M Limits
50 10 2 25 45 2 25 45 10 25 05 06
b2 0 b1 0 b0 5 b1 2
IDN
IDP
IDP
II
10
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 IDN and IDP are tested one output at a time