TSMC 0.25和0.35um 设计规则

2设计规则
2.1 设计规则几何关系定义
Width：
Sapcing:
Extension：一几何图形内边界到另一图形外边界长度
Overlap：一几何图形内边界到另一图形内边界长度
2.2设计规则
[TSMC_0.35_4M2P_SUBM] lambda＝0.2um [TSMC_0.25_5M1P_DEEP] lambda＝0.12um
2.2.1 Well [1.1-1.4]
2.2.2 Active [2.1-2.5]
2.2.3 Thick Active [24.1-24.5]
THICK_ACTIVE is a layer used for those processes offering two different thicknesses of gate oxide (typically for the layout of transistors that operate at two different voltage levels). The ACTIVE layer is used to delineate all the active areas, regardless of gate oxide thickness. THICK_ACTIVE is used to to mark those ACTIVE areas that will have the thicker gate oxide; ACTIVE areas outside THICK_ACTIVE will have the thinner gate oxide.
2.2.4 Poly [
3.1-3.5]
2.2.5 Silicide Block [20.1-20.9]
2.2.6 Select [4.1-4.4]
2.2.7 Electrode for Capacitor [11.1-11.6]
The poly2 layer is a second polysilicon layer (physically above the standard, or first, poly layer). The oxide between the two polys is the capacitor dielectric. The capacitor area is the area of coincident poly and electrode.
2.2.8 Electrode Contact [1
3.1-13.5]
The poly2 is contacted through the standard contact layer, similar to the first poly. The overlap numbers are larger, however.
2.2.9 Contact to Poly [5.1-5.4]
2.2.10 Contact to Active [6.1-6.4]
2.2.11 Metal1 [7.1-7.4]
2.2.12 Via [8.1-8.5]
2.2.13 Metal2 [9.1-9.4]
2.2.14 Via2 [14.1-14.4]
2.2.14 Metal3 [15.1-15.4]
2.2.15 Via3 [21.1-21.3]
2.2.16 Metal4 [21.1-21.4]
2.2.17 CAP_TOP_METAL [28.1-28.6]
The CAP_TOP_METAL layer is used exclusively for the construction of metal-to-metal capacitors. The bottom plate of the capacitor is one of the regular metal layers, as specified below. CAP_TOP_METAL is the upper plate of the capacitor; it is sandwiched physically between the bottom plate metal and the next metal layer above, with a thin dielectric between the bottom and top plates.
The CAP_TOP_METAL can only be contacted from the metal above; the bottom plate metal can be contacted from below or above (subject, in either case, to rule 28.5). CAP_TOP_METAL must always be contained entirely within the bottom plate metal.
2.2.18 Via4 (DEEP) [25.1-25.3]
2.2.19 Metal5 (DEEP) [26.1-26.3]
TSMC工艺设计规则] 2.2.20 Overglass [10.1-10.5]
Note that rules in this section are in units of microns. They are not "true" design rules, but they do make good practice rules. Unfortunately, there are no really good generic pad design rules since pads are process-specific.
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